electronics Article A Low-Complexity Edward-Curve Point Multiplication Architecture Asher Sajid 1 , Muhammad Rashid 2, * , Malik Imran 1 and Atif Raza Jafri 3   Citation: Sajid, A.; Rashid, M.; Imran, M.; Jafri, A.R. A Low-Complexity Edward-Curve Point Multiplication Architecture. Electronics 2021, 10, 1080. https:// doi.org/10.3390/electronics10091080 Received: 21 March 2021 Accepted: 26 April 2021 Published: 3 May 2021 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affil- iations. Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). 1 Science and Technology Unit (STU), Umm Al-Qura University, Makkah 24382, Saudi Arabia; malikasher267@gmail.com (A.S.); mlk.imran88@gmail.com (M.I.) 2 Department of Computer Engineering, Umm Al-Qura University, Makkah 24382, Saudi Arabia 3 Electrical Engineering Department, Bahria University, Islamabad 44000, Pakistan; atifraza.buic@bahria.edu.pk * Correspondence: mfelahi@uqu.edu.sa Abstract: The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over GF(2 233 ). There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-bit finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over GF(2 233 ) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 μs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time. Keywords: elliptic curve cryptography; binary edward curves; point multiplication; hardware architecture; area optimization 1. Introduction The internet-of-things (IoT) concerns a global network, where billions of heteroge- neous devices are required to connect with an unsecured internet [1]. The connected devices share information (or) data with each other. Since most of the devices in an IoT framework have constrained resources, data are usually stored in the cloud [2]. As a result, the users can continuously upload and download data from anywhere using the internet [3]. Due to this enormous communication of IoT devices through a cloud, they are subject to malicious attacks [4]. Security concerns arise, and therefore various threats and attacks may occur as data owners have no control over the data management [5]. Consequently, the importance of data security and the availability of limited resources provoke us to explore recent low-complexity cryptographic schemes [6]. Elliptic-curve cryptography (ECC), a public-key cryptography scheme, has become an attractive approach to target many applications like IoT security [7]. The main motivation behind the wide spread adoption of ECC is its ability to provide a similar security level with a relatively smaller key-sizes [8]. It comprises of four layers [9]. The top most layer (fourth layer) is the protocol layer which ensures the encryption and decryption of data. In layer three, the scalar (or) point multiplication (PM) is computed which is the most critical operation. For PM computation, the point addition (PA) and point doubling (PD) operations are performed in layer two. Finally, the layer one of ECC consists of finite-filed (FF) arithmetic operations (addition, multiplication, square and inversion). In addition to Electronics 2021, 10, 1080. https://doi.org/10.3390/electronics10091080 https://www.mdpi.com/journal/electronics