International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 International Conference On Emerging Trends in Mechanical and Electrical Engineering (ICETMEE- 13th-14th March 2014) Rustamji Institute of Technology 59 | Page CMOS Domino Logic Circuit for High Speed Performance Shiksha Kamal Kant Kashyap Shool of VLSI design Department of Electronics and and embedded system communication NIT Kurukshetra NIT Kurukshetra Kurukshetra, India Kurukshetra, India Email: shiksha.iet@gmail.com Email: kamalkant7185@gmail.com Abstract In this paper a high speed and low power domino logic circuit is proposed by using voltage divider current mirror technique. To avoid charge leakage and charge sharing problems, domino logic design is used in the circuit due to their advantages such as high speed and less noise immunity. Using this voltage divider current mirror circuit, contention current and power dissipation in the circuit is reduced without affecting the noise immunity of the circuit. With the scaling in technology, performance of digital logic is degrades due to increase in sub-threshold current. This proposed circuit provides very small speed-power product as compared to previously designed domino logic circuits. Simulations are carried out in cadence 90nm technology with supply voltage of 1 volt for the case of OR gate. Keywords: evaluation phase, pre-charge phase,dynamic node, robustness I. Introduction Domino logic circuits with wide fan-in are widely used in digital circuit designs due to their high speed and less number of transistors. Footless domino gate is most popular due to their less transistors count and better performance in comparison with static CMOS [1][2][3]. Footless domino gates are very simple to be realized in case of wide fan-in. Wide fan-in footless domino logic are often implemented in data-path in microprocessors, digital signal processing and digital memories. There are different sources in digital circuits. Most common noise sources are crosstalk, variation in supply voltage, charge leakage and charge redistribution [4]. The most effective way to reduce power dissipation is to reduce supply voltage. However on reducing supply voltage, threshold voltage is also reduced, which leads to increase in sub-threshold current exponentially [5]. The dynamic node of domino gate is affected by noise during evaluation phase. Dynamic node of domino gate can still discharge through Pull Down Network due to phenomena of charge leakage, charge redistribution and charge sharing [6]. Due to leakage current and noise in pull down network dynamic node of domino logic is discharged in evaluation phase. To hold the state of dynamic node during evaluation phase, keeper circuit is used at dynamic node. Generally a PMOS transistor is used in feedback as keeper circuit [7][8]. PMOS keeper prevents the charge stored at dynamic node during evaluation phase, when the inputs of pull down network are zeros. However, if the intensity of sub-threshold current is high keeper may not be able to maintain charge at the dynamic node. Keeper circuit provides contention current and thus degrades the performance of circuit. Due to generation of contention current short-circuit power is dissipated in the keeper circuit [9]. Keeper circuitry should be designed such that it will provide high performance, minimum contention current, less power consumption, less area and robustness. The basic dynamic domino gate is shown in fig1. When clk is low, M p is turned ON, dynamic node charges to V dd and circuit is in pre-charge state. Because M n is turned OFF, there does not exist any path to ground. When clk is high, transistor During evaluation phase, there are two conditions for the output voltage. If inputs IN1 and IN2 are equal to one, the dynamic node value is equal to zero and output of the circuit will be equal to one. When both input values are equal to zero, dynamic node voltage should be maintained at high value and output of the circuit should be zero. In this proposed scheme of domino logic, voltage divider current mirror circuit is used to RESEARCH ARTICLE OPEN ACCESS