A Soft Error Tolerant LUT Cascade Emulator Hiroki Nakahara and Tsutomu Sasao Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan Abstract An LUT cascade emulator realizes an arbitrary sequen- tial circuit. Given a sequential circuit, we convert the com- binational part into one or more LUT cascades, and store LUT(cell) data into a memory in the LUT cascade emula- tor. The emulator evaluates multi-output logic functions by reading cell data sequentially. To improve the tolerance to soft errors, cell data in the memory are encoded by er- ror correcting codes. Also, error-correcting circuits and checking circuits that periodically scan the memories are appended. When a soft error is detected, it removes the er- ror by rewriting the correct data into the memory. To mask soft errors in flip-flops, a TMR (Triple Module Redundancy) technique is employed. Our system detects a soft error in a single bit. Also, the mission time of the system is more than 1000x of time of an ordinary LUT cascade emulator. 1 Introduction With the decrease of the feature size of LSIs, the de- crease of the reliability that comes from the variation of devices or random failure, becomes the problem [8]. Soft errors induced by thermal neutrons, cosmic rays, or alpha particles hitting the surface of silicon devices at random, are irreproducible [7]. Soft errors are the major causes of random failure. With the reduction of supply voltage and the size of transistors, the electric charge stored in a semi- conductor element also decreases. The amount of critical electric charge that flips the data also decreases. As a re- sults, soft errors occur not only in the outer space, but also on the ground. Furthermore, the frequently of soft errors is not negligible [14]. Many methods to prevent soft errors exist [15]. One method is to use radiation-hardened devices. However, such devices are much more expensive than ordinary de- vices. Furthermore, the performance of radiation-hardened devices is several generations behind state-of-the-art de- vices. A realistic, low-cost and high-performance solution is to add redundancy to the circuits. SRAMs, where each word is encoded by an ECC (Error Correcting Code), can detect and correct soft errors. Since a soft error does not destroy the semiconductor device, we can remove the soft error by rewriting the correct data to it. For SRAM-based FPGAs, a technique that periodically checks the configu- ration data has been developed [5]. When it detects a soft error in the FPGA, it rewrites the configuration bits. We have proposed a look-up table (LUT) cascade em- ulator. An LUT cascade, where multiple-output LUTs are connected in series, realizes a multiple-output function [19]. An LUT cascade emulator consists of a control part, mem- ories, and registers. Each register is connected to the pro- grammable interconnection circuit, and the LUT cascade emulator evaluates the logic circuit stored in the mem- ory [19]. The LUT cascade emulator realizes an arbitrary sequential circuit by storing logic data and its interconnec- tion data in memories. Compared with an ordinary mi- croprocessor, the LUT cascade emulator is about 10 times faster, while its power consumption is smaller. Compared with FPGAs, the LUT cascade emulator is several times slower, and power dissipation is larger. However, since the place and routing design in the LUT cascade emulator is unnecessary, the design time for the LUT cascade emula- tor is shorter than FPGAs, and the delay estimation for the LUT cascade emulator is also more accurate than that of FPGAs. By applying the method described later in this paper, the mission time of the LUT cascade emulator can be improved. For soft errors, our LUT cascade emulator only need to rewrite a part of the memory, while an FPGA needs to rewrite all the configurations. In this paper, we will present a soft error tolerant LUT cascade emulator. The rest of the paper is organized as follows: Section 2 presents the LUT cascade emulator. Section 3 presents error models of the LUT cascade emulator. Section 4 presents the soft error tolerant LUT cascade emulator. Section 5 evalu- ates the reliability of the proposal method. Finally, Section 6 concludes the paper. 2 LUT Cascade Emulator 2.1 LUT Cascade An LUT cascade is shown in Fig. 1, where multiple- output LUTs (cells) are connected in series to realize a