IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 9, SEPTEMBER 2011 2903 Theory of the Junctionless Nanowire FET Elena Gnani, Member, IEEE, Antonio Gnudi, Member, IEEE, Susanna Reggiani, Member, IEEE, and Giorgio Baccarani, Fellow, IEEE Abstract—In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction- based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical under- standing of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excel- lent ON-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor. Index Terms—Depletion-mode field-effect transistor (FET), junctionless field-effect transistor (JL-FET), nanowire field-effect transistor (NW-FET), subthreshold slope (SS). I. I NTRODUCTION C URRENT transport in nanowire field-effect transistors (NW-FETs) has been the subject of several investiga- tions, both analytical and numerical. Analytical models typi- cally rely on two basic assumptions, namely, 1) an undoped semiconductor nanowire and 2) Boltzmann statistics [1]–[7]. These assumptions allow, in fact, for a closed-form solution of Poisson’s equation [1], [2], which makes it possible to work out an intrinsic analytical relationship between gate voltage and surface potential. Alternatively, the assumption is taken of a completely depleted nanowire, consistently with the inves- tigation of subthreshold slope (SS) and short-channel effects (SCE) [8]. More recently, a study on the gate capacitance of surrounding-gate NW-FETs has been carried out accounting for acceptor-type doping [9] so that carriers are confined only within the inversion layer. Numerical approaches, instead, ac- count for nearly all of the relevant effects that exert an impact on the device behavior, including motion quantization, subband splitting, Fermi statistics, quasi-ballistic transport, surface and channel orientation, and band structure [10]–[13]. Recently, Manuscript received March 15, 2011; revised May 3, 2011; accepted June 1, 2011. Date of publication July 14, 2011; date of current version August 24, 2011. The review of this paper was arranged by Editor M. A. Reed. The authors are with the “E. De Castro” Advanced Research Center on Electronic Systems (ARCES), University of Bologna, 40125 Bologna, Italy, and also with the Department of Electronics, Computer Sciences and Systems, University of Bologna, 40136 Bologna, Italy (e-mail: egnani@arces.unibo.it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2159608 a junctionless (JL) NW-FET with a high content of impurity concentration within the channel and source/drain (S/D) regions has been proposed, and a device model based on the abrupt- depletion approximation has been worked out [14], [15]. Soon after, a JL silicon-on-insulator (SOI) FET was fabricated and characterized by the Tyndall group [16]–[18]. The idea behind this device is that of drastically simplifying the S/D engineering by removing the related junctions, as well as the S/D extension regions while, at the same time, appropriately sizing the silicon thickness and the doping density in order to allow its switching on and off under the gate control. The fabricated devices exhibit excellent turn-on and output characteristics [16], [17] with a nearly ideal SS ≃ 60 mV/dec, a large ON-current, which is quite comparable with that of an undoped channel transistor with the same geometry, a very small drain-induced barrier lowering (DIBL), and an interesting temperature behavior [18] owing to the moderate temperature sensitivity of the carrier mobility at large impurity concentrations. It is the purpose of this paper to investigate the theoretical foundations of the JL NW-FET with the aim to better under- stand the behavior of this device, to clarify the motivations for its surprisingly good properties, and to elucidate its strengths and weaknesses. Being a depletion/accumulation device with a high doping content in the channel, a nearly ideal SS is especially surprising. The model worked out here, however, does not rely on the abrupt-depletion approximation but, rather, on the linearization of the electric potential in the region where an appreciable content of electronic charge is present. In doing so, we achieve a better solution of Poisson’s equation, which allows us to obtain an accurate description of the internal po- tential and a continuous drain current at the transition between subthreshold and the ON state. This paper is organized as follows: Section II addresses the basic relationship between gate voltage and surface po- tential for a cylindrical geometry. Section III is devoted to the solution of Poisson’s equation within a classical model under the assumption of Boltzmann statistics. For a doped semiconductor, even the first integral of Poisson’s equation is not available in closed form. Therefore, a regional approach is used by a separate consideration of the accumulation and depletion conditions. In Section IV, we investigate the ON-state device characteristics and compare the model with numerical results. Section V is devoted to a simplified calculation of the subthreshold current, with a novel expression for the preexpo- nential factor, which holds for any doping density. Section VI discusses the strengths and the limitations of the JL NW-FETs for future technology developments, and Section VII draws some conclusions. Finally, an appendix illustrates a simplified calculation of the drain current in depletion. 0018-9383/$26.00 © 2011 IEEE