Retrieval Number: B3575078219/19©BEIESP DOI: 10.35940/ijrte.B3575.078219 International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-2, July 2019 5936 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Abstract: The demand for low power processor is increasing day by day in mobile application for video, audio, mixed signal processing, gaming console and battery-operated electronic devices. Power consumption is the main issue in batter operated devices which constantly reduces battery life. Compared to static power Dynamic power yields more power consumption in digital design. Clock power is one of the major factors in total power consumption which results in high dynamic power consumption. In this paper, a 32-bit MIPS processor is designed to maximize the performance while considering the battery life of the device. Clock gating and data gating method is adopted in this paper and to reduce dynamic power. This design is implemented on 28nm kintex-7 FPGA Board and power is analyzed Index Terms: MIPS, power consumption, dynamic power, clock gating, switching activity. I. INTRODUCTION MIPS architecture is the most efficient RISC architecture which delivers best performance with low power consumption in a given silicon area. MIPS is one of the three CPU architectures which provide great support to Android base devices, linux and RTOS, it is best rated among google android devices. MIPS is generally designed for high performance application with low power consumption. Electronic devices with high performance release a large amount of heat which is a practical limitation to enhance the performance of system. Designers need to consider the factors which influence the system performance and also should consider time to market. FPGA devices are the best solution for better time to market because of re-programmability feature in FPGA. In recent year, number of researchers are implementing various microprocessors using FPGA with high performance, low power and cost for portable devices. In digital design speed of the processor is major concern to improve performance of the device and as speed is inversely proportional to power so trade-off is required between speed and power. As the design size increases switching activity in MIPS processor will result in more dynamic power. With the scaling of technology, power-density is increased. In CMOS technology the real challenge is to scale voltage and frequency beyond 65nm, because with decrease in nano meter technology results in higher dynamic and leakage Revised Manuscript Received on July 09, 2019 V.Prasanth, Ph.D Scholar, Jawaharlal Nehru technological University, Kakinada, Andhra Pradesh, India. K.Babulu, Professor of ECE, Jawaharlal Nehru technological University/ Kakinada, Andhra Pradesh, India M.Kamaraju,Professor, Electronics and communication Engineering Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India. current density with minimal improvement in speed. In Modern design both in logic and memory static and dynamic power is increasing drastically. Clock power is the dominant power which consumes 50-60 percent of total power and it increases significantly with improvements to the next generation of designs at 90nm and below [6]. As a fact that power is directly proportional to voltage (V) and the frequency of the clock(F) as shown in the following equation    Clock gating is most effective method for reducing dynamic power by limiting switching which saves clock power[2]. Clock gating is generally implemented at gate-level synthesis tool. The main challenge in chip design for optimizing power is to know where and when to insert clock gating. II. MIPS ARCHITECTURE The MIPS architecture is created from research on efficient processor organization and VLSI integration at Standford University; it is designed with five stage execution pipeline and cache controller on a single silicon chip. MIPS architecture has five stages: fetch, decode, execute, memory-access, write back. Fig 1: MIPS five-stage The key concepts of MIPS architecture are  Five-Stage Execution  32 bit instruction set  3 operand logic and arithmetical instruction  Thirty-two, 32 bit general purpose register  Only load and store instruction access memory Dynamic Power Optimization of 32 Bit MIPS Processor Using Clock Gating For Low Power Applications V.Prasanth, K.Babulu, M.Kamaraju