Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol. 7, No. 2, June 2019, pp. 357~365 ISSN: 2089-3272, DOI: 10.11591/ijeei.v7i2.1041  357 Journal homepage: http://section.iaesonline.com/index.php/IJEEI/index Effect of clock gating in conditional pulse enhancement flip-flop for low power applications Kuruvilla John 1 , Vinod Kumar R. S. 2 , Kumar S. S. 3 1,2 Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, India 3 Department of Electronics and Instrumentation Engineering, Noorul Islam Centre for Higher Education, India Article Info ABSTRACT Article historys: Received Feb 14, 2019 Revised Apr 30, 2019 Accepted May 20, 2019 Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip- flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip- flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P- FFs. Its maximum power saving against conventional designs is up to 30.65%. Keywords: Clock gating Conditional discharging Implicit Low power Pulse flip-flop Copyright © 2019 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Kuruvilla John, Research Scholar, Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thucklay, Tamilnadu, India, 629180. Email: kuruvilla08@gmail.com 1. INTRODUCTION In all kinds of digital structures flip-flops are widely used as the basic storage element. It is also estimated that above 25% of the total system power is consumed by the clock system [1]. Thus, FFs contributes a major part of the power consumption of the total system. P-FF exhibits better performance than conventional master-slave FF designs in low power and high-speed applications [2]. The single latch structure design of P- FFs made them more popular than conventional master-slave and transmission gate-based FF designs in low power and high-speed applications [3]. The generator and latches are the basic parts in the structure of a P-FF design are pulse. The trigger pulses are generated by the pulse generator which may be generated either at any edges of clock signals or at both edges of clock signals. The latch structure performs the latching or sampling of the input data into the output based on the generation triggering pulses. Depending upon the pulse generation mechanism, P-FFs are classified as a single and double edge triggered types [4]. Based on the connection of pulse generation logic and latch, P-FFs are classified as implicit and explicit types [5]. In implicit case, the pulse generator is inbuilt in the latch structure and in explicit it is external to the latch structure. It is estimated that due to the control of discharging path the implicit P-FFs are more power efficient than explicit types [6-8]. However, the sharing of pulse generator among neighboring latches is an advantage of explicit P-FF. Both implicit and explicit P-FFs face the longest discharging path problem in the latch structure. This increases the size of the transistors used at the pulse generator to enlarge the width and height of triggering pulses for the sufficient capturing of data. brought to you by CORE View metadata, citation and similar papers at core.ac.uk provided by Indonesian Journal of Electrical Engineering and Informatics (IJEEI)