264 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 2, JUNE 2004 A Nanoscale Memory and Transistor Using Backside Trapping Helena Silva and Sandip Tiwari, Fellow, IEEE Abstract—We report results on a new structure that provides a scalable memory cell and a scalable transistor simultaneously in the same structure. The operational distinction is achieved through a difference in the bias range. The device employs a modified sil- icon-on-insulator substrate where charge is stored in a defected region underneath a thin single-crystal silicon layer employed for the formation of the transistor channel. At low voltages (below 1.5 V), the device operates as a transistor making use of the front silicon interface (preferred form), or the back interface, or both. The memory operation is obtained by use of high voltages, which allow injection of charge into the defected region in a stack of in- sulating films underneath the thin silicon channel, as well as the removal of the charge. The transistors are scalable because of the thin silicon technology and the memories are highly scalable be- cause they allow efficient coupling between the carriers and storage region. The structure provides for a very useful decoupling of the memory read and transistor operation from the memory electrical storage operation. The experimental operation of the devices is de- scribed. Index Terms—Back-floating gate, CMOS device scaling, EEPROM, flash memories, nonvolatile memory, scaling limits, semiconductor memories, silicon-on-insulator (SOI) technology, silicon–oxide–nitride–oxide–silicon (SONOS) memory, tunneling. I. INTRODUCTION M ANY OF THE electronic applications employ logic together with nonvolatile memory, either through silicon integration such as in system-on-chip or through hybrid integration. The nonvolatile memory, in such applications, serves as the source of microcode, other operating code, or for other stored information that needs to be downloaded for the necessary computation being performed through logic and faster forms of memory such as static random access memories. Whereas MOSFET transistors appear to be on a path of scaling to the 10-nm-length scale [1] through judicious control of electrostatics and parasitics, conventional silicon nonvolatile memories (flash memories), based on front poly-silicon floating gates, do not follow this path of scaling with 90 nm [2] as the length scale for the most aggressive devices reported today. The difficulties of making smaller silicon nonvolatile mem- ories with the conventional geometries arise from the fact that Manuscript received November 21, 2003; revised January 17, 2004. This work was supported by the National Science Foundation (NSF) under the Cornell Center for Materials Research and the Foundation for Science and Technology, Portugal. The fabrication was performed at the Cornell Nanoscale Facility, which is supported by the NSF under the National Nanofabrication Users Network. This paper was presented in part at the 2003 IEEE Silicon Nanoelectronics Workshop. The authors are with the School of Applied and Engineering Physics, Cornell University, Ithaca NY 14853 USA (e-mail: hgs4@cornell.edu). Digital Object Identifier 10.1109/TNANO.2004.828532 the gate stack (injection oxide, poly-silicon gate, and control oxide) cannot be thinned as required for small gate-length de- vices without compromising the memory performance. Smaller gate-length devices require thinner gate oxides for efficient con- trol of the channel by the gate. In conventional flash memo- ries, however, since the charge is stored between the channel and front gate, the thinning of the gate stack, injection, and control oxides is intrinsically coupled to issues related to the memory function, namely, retention time and reliability of the device. Also, from a low-voltage and low-power perspective, a thinner gate oxide will allow faster writing and erasing times and lower programming voltages, but worsen the retention time and reliability due to increased charge leakage. The hot-elec- tron injection (HEI) coupling to the floating gate also degrades at small gate lengths because hot carrier mean free paths are in the 10–40-nm range and a larger fraction of the hot carriers oc- curs in the drain junction region with the scaling of the physical gate length. Currently, it appears that in order to make smaller lower voltage and lower power silicon nonvolatile memories, al- ternative device structures or programming mechanisms need to be developed. High-density, isolated, and localized charge storage centers, such as dielectric defects or semiconductor nanocrystals, may provide such alternatives for silicon nonvolatile memories. As compared to a continuous conducting plate like in the current flash devices, isolated storage centers can be placed closer to the channel, resulting in a thinner gate stack with which small gate-length devices can be implemented. Car- rier trapping through defects and interface states has been successfully utilized in silicon–oxide–nitride–oxide–silicon (SONOS) memories [3], where charge is stored in defects at the oxide–nitride interface and within the nitride film, and these devices seem to be promising candidates for reduced dimension storage nonvolatile memory technology. Scaling of SONOS memories has been the focus of intensive research over the past years [4], [5] with significant improvements reported. However, the structure of the conventional SONOS memories, where the trapping layer still exists between the channel of the device and gate, continues to impose restrictions on scaling of these devices because of the interdependence of electrostatics, voltages needed for adequate programming, speed, capture cross sections, erasing speed, and nonvolatility. Here, we report on experimental results of a new structure [6] where the charging and discharging occurs through a trap- ping layer formed by a stack of insulating films similar to that of SONOS (an oxide–nitride–oxide (ONO) stack in the example reported here) that is placed on the back of a thin silicon channel. Conceptually, this is similar to that employed in back floating 1536-125X/04$20.00 © 2004 IEEE