IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 58, NO. 1, FEBRUARY 2016 249 Predicting Statistical Characteristics of Jitter Due to Simultaneous Switching Noise Chunchun Sui, Student Member, IEEE, Liehui Ren, Student Member, IEEE, Xu Gao, Student Member, IEEE, Jingnan Pan, James L. Drewniak, Fellow, IEEE, and Daryl G. Beetner, Senior Member, IEEE Abstract—Switching of logic gates is often responsible for signif- icant power supply noise. Predicting the jitter resulting from the power supply noise can be critical to analyze the proper opera- tion of high-speed devices. The statistical characteristics of jitter, such as the mean standard deviation of jitter, can be used to place a meaningful bound on the worst-case timing margin and to es- timate the bit error rate. While the statistical characteristics of the noise can be found through simulations of many input logic vectors, such simulations require significant computational effort and require methods for choosing suitable data vectors. Vectorless methods allow rapid analysis of switching without using predefined input data and can be used to understand which portions of the logic circuit contribute most to the noise. In this paper, methods using vectorless techniques are presented to predict the mean and standard deviation of the power supply noise on the printed circuit board (PCB), and the mean and standard deviation of the resulting peak-to-peak jitter in a driver on the same PCB. In experiments, the techniques were able to predict the average and standard devi- ation of the peak power supply noise on the PCB with 2% and 8% error, respectively, and of the peak-to-peak jitter with 21% error, which is sufficient for predicting how a specific logic design might impact jitter, and for proposing means to minimize that impact. Index Terms—Analytical models, field programmable logic ar- ray, integrated circuit (IC) noise, jitter, noise measurement, power distribution, statistical analysis. I. INTRODUCTION A S the speed of integrated circuits (ICs) grows and timing margins shrink, signal integrity issues become increas- ingly important to an IC design [1] and raise-up critical require- ments for system optimizations [2], [3]. Power supply noise can have a major impact on the signal integrity, as an increase in the noise can result in an increase of the jitter [4]. Switching of logic gates at clock edges is responsible for significant power supply noise. An ability to predict bounds on the noise and the resulting jitter could allow the engineer to account for the jitter Manuscript received January 28, 2015; revised June 27, 2015; accepted Au- gust 18, 2015. Date of publication December 29, 2015; date of current version February 16, 2016. This work was supported in part by the National Science Foundation under Grant IIP-1440110. C. Sui and L. Ren were with the Department of Electrical and Computer Engineering, Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO 65409 USA. They are now with Cisco Systems, Irvine, CA 92617 USA (e-mail: csdh8@mst.edu; lrzn6@mst.edu). X. Gao was with the Department of Electrical and Computer Engineering, Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO 65409 USA (e-mail: xg2z7@mst.edu). J. Pan, J. L. Drewniak, and D. G. Beetner are with the Department of Elec- trical and Computer Engineering, Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO 65409 USA (e-mail: jpfz6@mst.edu; drewniak@mst.edu; dary1@mst.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TEMC.2015.2474124 and could be used to develop improved designs with less jit- ter and lower bit error rate. Predicting the jitter caused by the noise from a particular logic design, however, is challenging. It requires a method to estimate the reasonable worst-case switch- ing current consumed by the logic, a method of predicting the noise voltage resulting from the dynamic current consumed by the logic, and a method for predicting the jitter from the resulting noise. While vector-based methods are available for predicting the power supply noise caused by switching in the logic [5], vector-based methods require substantial computational effort, since many vectors must typically be simulated [6]. Finding ap- propriate vectors is challenging, particularly early in the design process. The goal of this paper is to develop a method using vectorless techniques to predict the statistical characteristics of timing jitter due to simultaneous switching noise. The statistical characteristics can be used to place bounds on the expected jitter and improve the logic design. Prediction of simultaneous switching noise has been a topic of several recent studies. Power supply noise can be found through simulations [5] or from closed-form expressions [7]. Power sup- ply noise from logic implemented in a field programmable gate array (FPGA) was predicted in [5]. Prediction was enabled with a high-frequency model of the power delivery network (PDN) of the die, package, and printed circuit board (PCB). The PCB was modeled using a cavity structure. Switching current was determined through simulations in Quartus II of the power con- sumed by the logic when responding to specific input data [8]. This paper demonstrated that the power supply noise can be modeled precisely when given sufficient information about the PDN and the IC switching currents. Similar results were found in [9]. Input data vectors, however, are not always available and simulating many random vectors is computationally expensive. Vectorless methods are computationally efficient and do not require known input data vectors [10]. Results are predicted us- ing the statistical likelihood of a switching event, rather than on exercising logic with specific input vectors. These methods are typically used to predict the power consumed by a logic design. As such, most vectorless methods only find the average switch- ing rate and the average current. In [11], methods were presented for determining the variance of switching and of current from clock-to-clock. Calculating both the mean and variance allows precise statistical bounds to be place on peak current or power consumption. These techniques will be used here to statistically characterize the power supply noise. The relationship between power supply noise and jitter is well known. A method to correlate simultaneous switching noise with signal jitter was presented in [12]. This paper studied how the PDN impedance affects signal jitter and voltage margin. A similar study in [13] and [14] showed that the output jitter peaks 0018-9375 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.