INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 9, ISSUE 01, OCTOBER 2019 ISSN 2277-8616 2277 IJSTR©2019 www.ijstr.org Design and Reliability Analysis of Reliable Irregular Shuffle Exchange Network (RISEN) Shobha Arya, Nipur Singh Abstract— The performance of multiprocessor systems, parallel and distributed systems depends on its interconnection networks. The Multistage Interconnection Network (MIN) is an interconnection network in which predefined topology has several layers of systematic interlinked switching elements (SE) that allow processors and memory modules to communicate with each other. This paper examines the reliability of the proposed network named as Reliable Irregular Shuffle Exchange Network (RISEN) and compares it with the existing Irregular Augmented Shuffle Exchange Network-4 (IASEN-4). Routing algorithm shows that RISEN is a multipath Multistage Interconnection Network (MIN) which can withstand faults and provides alternate paths between a source-destination pair with dynamic rerouting ability. The performance and comparison analysis exhibit that the proposed RISEN is more reliable and fault tolerant as compared to the existing MIN. Index Terms— Multistage Interconnection Network, Fault tolerance, Reliability, Switching elements ——————————  —————————— 1 INTRODUCTION Reliability, fault tolerance, and cost-effectiveness are the dominant issues in Multistage Interconnection Networks (MINs) performance. The reliability of MIN can be increased by handling more faults in various switching stages. MINs are faster, low-cost networks and they are used in Single Instruction Multiple Data (SIMD) and Multiple Instruction Multiple Data (MIMD) computers. Based on topologies the MINs can be classified as follows: Regular, Irregular, and Hybrid. The regular MIN consists of the same number of switching elements (SE) in each stage [15]. In irregular MIN, the number of switching elements (SE) is not the same in each stage [15]. The hybrid MIN consists of the properties of regular MIN as well as the properties of irregular MIN also [15]. The performance of MIN can be measured in terms of fault tolerance, reliability and permutation capability. The reliability can be classified into two types such as hardware reliability [12] and software reliability [11] [15]. The hardware reliability can be defined on the basis of time but software reliability cannot [11]. In hardware reliability, how much time the hardware remain functioning without any fault. In this paper, the focus is given to the hardware reliability of the MINs. Simple series-parallel probabilistic combinations, upper bound & lower bound of Mean Time to Failure (MTTF) are used to compute reliability [15]. MTTF of RISEN is measured through the criterion of “full access” and “switch fault or dead-fault” model. The full access criterion implies the ability to reach from any input to any output precisely in one pass even some switching components or segments (crossbar switches, MUX, DEMUX) may be defective or faulty but not the whole network [13][15] and this failure of segments doesn’t influence the reliability of others for example switch failure occurs individually. In switch-fault or dead fault model, failure or fault in a switch makes it totally ineffective and non-working [13][15]. MTTF is the expected time elapsed before some source is disconnected from some destination [13][14][15]. A limited work has been done on the reliability of irregular MINs [8],[9],[10][13]. In this paper, we are focusing on existing irregular MIN named as Irregular Augmented Shuffle Exchange Network-4 (IASEN-4)[14] and create a modified MIN named as Reliable Irregular Shuffle Exchange Network (RISEN). The main drawback of IASEN-4 is less reliability and having less alternate paths between any source-destination pair with less accessibility [1] in non-faulty (when there is no faulty node in each stage) and faulty (when a faulty node exists in one or more stages) cases. Therefore, a new MIN named as Reliable Irregular Shuffle Exchange Network (RISEN) has been proposed to resolve this issue. RISEN is more reliable and it provides more alternate paths in faulty and non-faulty cases. This paper addresses the issue of reliability and improves the performance of the proposed network by reducing the count of links in the proposed RISEN. We compared the reliability of proposed RISEN with existing Irregular Augmented Shuffle Exchange Network-4 (IASEN-4). In section 2, the structure of existing MIN (IASEN-4) and proposed MIN (RISEN) has been described. The generalized link connection formula is also given for RISEN in each stage. Section 3 describes the routing scheme of RISEN in which redundancy graph and routing algorithm is given. Section 4 describes the reliability analysis of existing and proposed MINs. Section 5 concentrates on the cost-effectiveness of both MINs. At last conclusion has been described in section 6. 2 STRUCTURE AND DESIGN OF MINS The structure of the existing IASEN-4 and proposed RISEN are discussed below 2.1 Irregular Augmented Shuffle Exchange Network-4 (IASEN-4) IASEN-4 is an N×N network which consists of N sources, N destinations, N Multiplexers (MUX) and N Demultiplexers (DEMUX) with (log 2 N/2) stages [14]. The first and last stage consists of 2 n-1 switching elements (SE) whereas intermediate stages consist of the 2 n-2 number of switching elements (SE), where n=log 2 N. The size of MUX and DEMUX is 4x1 and 1x4 respectively. The first stage, intermediate stage, and last stage have SEs of size 2x3, 4x2, and 2x2 respectively. SEs of each stage is associated with each other through alternative links [14]. 2.2 Reliable Irregular Shuffle Exchange Network (RISEN) The Reliable Irregular Shuffle Exchange Network (RISEN) has N sources and N destinations, which are connected, with N multiplexers (MUX) and N demultiplexers (DEMUX) respectively. The size of each MUX and DEMUX in RISEN is 4×1 and 1×4 respectively. RISEN has n number of stages, range from 0 to (n-1), where n= log 2 N. Stage 0 and last stage consist of (N/2) number of switching elements (SE). There are (n-2) middle stages (m) in the network. Each middle stage (m) consists of N/4 number of SEs. In stage 0, each SE is attached with two MUX of size 4x1 and in the last stage; two DEMUX of size 1x4 are connected with each SE. The SEs of