How Much Cost Reduction Justifies the Adoption of Monolithic 3D ICs at 7nm Node? Bon Woong Ku † , Peter Debacker § , Dragomir Milojevic § , Praveen Raghavan § , and Sung Kyu Lim † † School of ECE, Georgia Institute of Technology, Atlanta, GA § IMEC, Leuven, Belgium bwku@gatech.edu, sklim@ece.gatech.edu ABSTRACT In this paper we study power, performance, and cost (PPC) trade- offs for 2-tier, gate-level, full-chip GDS monolithic 3D ICs (M3D) built using a foundry-grade 7nm bulk FinFET technology. We first develop highly-accurate wafer and die cost models for 2D and M3D to study PPC tradeoffs. In our study, both 2D and M3D designs are optimized in terms of the number of BEOL metal layers used for routing to obtain the best possible PPC values. We develop a new CAD methodology for 2-tier gate-level M3D, named Projected 2D Flow, that allows us to accurately compare RC parasitics of equiv- alent nets in both 2D and M3D designs. Our experiments based on two different circuit types (BEOL-dominant vs. FEOL-dominant) confirm that M3D designs indeed offer a significant footprint sav- ing. However, to our surprise, the PPC quality of M3D turns out to be worse than that of 2D by 34% due to the high wafer cost of M3D. Our study also reveals that M3D wafer yield should be as high as 90% of 2D wafer yield, and the M3D device manufacturing cost should be less than 33% of that of 2D to justify the adoption of M3D technology at the 7nm era. Lastly, and counter-intuitively, our study shows that FEOL-dominant circuit shows more PPC benefits from M3D technology than BEOL-dominant circuit. CCS Concepts •Hardware → 3D integrated circuits; Physical design (EDA); Methodologies for EDA; Yield and cost modeling; Keywords Monolithic 3D IC; Gate-level; Cost Modeling; 1. INTRODUCTION As 2D device scaling faces toward physical limitation, consid- erate efforts for 3D integration have been made to extend tech- nology scaling benefits. Over the last few years, monolithic 3D (M3D) technology, where active layers are implemented on top of the bottom tier sequentially, has emerged as a promising solution for the massive vertical interconnection. While through-silicon- via (TSV) based 3D integration requires chip-level or wafer-level Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full cita- tion on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or re- publish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. ICCAD ’16, November 07-10, 2016, Austin, TX, USA © 2016 ACM. ISBN 978-1-4503-4466-1/16/11. . . $15.00 DOI: http://dx.doi.org/10.1145/2966986.2967044 alignment process with μ m-scale precision, M3D integration ma- nipulates litho-scale alignment enabling extremely small size of the monolithic inter-tier vias (MIVs). These tiny MIVs not only have minimized area overhead, but also offer the inter-tier vertical con- nections in orders of magnitude. Therefore, effectively inserted MIVs significantly reduce wirelength of 3D nets resulting in huge power-delay benefits [1]. Depending on granularity of tier partitioning, M3D technology is categorized into transistor-level, gate-level, and block-level [2, 3, 4]. Out of these 3 types, gate-level M3D allows to harness dense vertical interconnections more than block-level M3D, resulting in sufficient wire length decrease in global routing. While transistor- level M3D requires additional efforts for new layout and character- ization of standard cells due to the split of PMOS and NMOS into different tiers, gate-level M3D allows to reuse existing 2D standard cell libraries for the full-chip GDS M3D ICs [3]. In this paper, we study power, performance, and cost (PPC) tradeoffs for 2-tier, gate-level, full-chip GDS M3D IC built on a foundry-grade 7nm bulk FinFET technology. Most of the earlier works on gate-level M3D have focused on power, performance, and area improvement in 2-tier design given the same routing resources as 2D IC, and no silicon area overhead. For example, if a 2D IC has 5 metal layers and 100mm 2 footprint, then 2-tier M3D IC has 5 metal layers and 50mm 2 footprint on top and bottom tiers each. Based on those assumptions, [5, 6, 7] shows that gate-level M3D ICs indeed offer huge iso-performance power saving compared with 2D ICs. Simply and ideally think- ing, 50% footprint saving in M3D ICs results in 29.3% wire length reduction (1/ √ 2 wire length scaling) if the design aspect ratio is assumed to be the same, and also if tier partitioning is done by placement-driven partitioning [8]. This wire length saving not only decreases wire capacitance (switching power saving) but also pro- vides path timing margin to reduce buffer counts (internal power saving). Therefore, if the type of a design is wire capacitance dominant circuit, power saving in gate-level M3D is expected to be more. However, since the footprint of wire capacitance dominant cir- cuit could be determined by routability of limited routing resources, the design quality of this type of circuit would be easily improved when we add more routing layers. While M3D design needs to have the number of metal layers as few as possible for the process cost reduction, adding more metal layers and optimizing Back-End-Of- Line (BEOL) metal stack in 2D IC can be easily achieved with reasonable cost overhead [9]. Therefore, it leads us to the next questions on how to set the proper 2D reference design for the fair PPC comparison with M3D design, and how much M3D has PPC- competitiveness to make us move toward M3D era. This paper addresses above questions.