168 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 2, FEBRUARY 2011 Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling Dae Hyun Kim, Student Member, IEEE, Saibal Mukhopadhyay, Member, IEEE, and Sung Kyu Lim, Senior Member, IEEE Abstract—In this paper, we present analytical models for fast es- timation of coupling capacitance of square-shaped through-silicon vias (TSVs) in three-dimensional integrated circuits (3D ICs). Er- rors between our model and Synopsys Raphael simulation on reg- ular TSV structures remain less than 6.03% while the computa- tion time of our model for capacitance estimation is negligible. We also develop a simple capacitance estimation technique to extract TSV-to-TSV coupling capacitance in general layouts. Average er- rors between our model and Raphael simulation on random TSV structures is 5.06%–8.24%, and maximum errors remain less than 18.91% which is tolerable for fast capacitance estimation in com- puter-aided design area. Index Terms—Capacitance, through-silicon via (TSV), timing analysis, three-dimensional integrated circuits (3D IC). I. INTRODUCTION D RIVEN by the need for performance improvement, a large number of universities and companies are actively researching 3D IC, which is expected to lead to shorter total wirelength, higher clock frequency, and lower power con- sumption than 2D IC [1]–[3]. In 3D IC, multiple dies are stacked, and vertical interconnections between dies are realized by through-silicon vias (TSVs). These TSVs play a central role in replacing long interconnects found in 2D ICs with short vertical interconnects. Shortened wires will result in low wire delay, thereby improving performance. In addition to performance improvement, it is also possible with 3D hetero- geneous integration to stack disparate technologies to provide a 3D structure with heterogeneous functions including logic, memory, MEMS, antennas, display, RF, analog/digital, sensors, and power conversion and storage. Therefore, universities and companies have been actively developing TSV manufacturing and die-to-die bonding technologies [4]–[9]. Moreover, various works on utilizing TSVs for physical design have also been proposed recently [10], [11]. Manuscript received June 22, 2010; revised October 08, 2010; accepted November 08, 2010. Date of publication January 20, 2011; date of current version March 23, 2011. This research is based upon the work supported by the National Science Foundation under CAREER Grant CCF-0546382 and CCF-0917000; the SRC Interconnect Focus Center (IFC), and Intel Corpora- tion. This work was recommended for publication by Associate Editor J. Kim upon evaluation of the reviewers comments. The authors are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2010.2101910 The basic electrical characteristics of TSVs such as resis- tance, capacitance, and inductance have also been investigated in the literature to provide circuit designers with physical anal- ysis and ranges of their values [12]–[16]. One of the results to notice is that TSV coupling capacitance is very big (tens of femto-farads) [13] so that it has huge impact on timing and in- terconnect power [17], [18]. Therefore, computer-aided design (CAD) tools are required to compute TSV coupling capacitance quickly but accurately during placement, routing, and optimiza- tion of timing and power in 3D ICs. TSV-to-TSV (or TSV-to-wire) coupling capacitance is af- fected by TSV-to-TSV (or TSV-to-wire) distance, TSV and wire dimensions, the number of surrounding TSVs and wires, and their spatial distribution. It is therefore almost impossible to use lookup tables to compute TSV capacitance quickly because too many variables exist. In addition, it is also almost impossible to use field solvers for TSV capacitance computa- tion during placement, routing, or optimization of timing and power because field solvers require nonnegligible amount of computation time. In this paper, we present an accurate analytical model for the coupling capacitance among square-shaped TSVs and wires. In order to model layouts accurately, we consider various types of coupling and fringe capacitances while taking neighboring TSVs and wires into account. Our experiments show that errors between our model and Synopsys Raphael simulation remain less than 6.03% on regular TSV structures, and average errors on random TSV structures remain less than 5.06%–8.24% while our model requires a fraction of runtime for capacitance com- putation. This paper is organized as follows. In Section II, we briefly discuss device structures in 3D ICs and review TSV coupling models. Section III shows basic formulas for capacitance com- putation. In Sections IV and V, we present our analytical models for fast estimation of TSV coupling capacitance. Capacitance estimation results on regular TSV structures and the impact of TSV capacitance on signal delay are presented in Section VI. We compare capacitances obtained from our model and Raphael simulation on random TSV structures in Section VII, and con- clude in Section VIII. II. DEVICE STRUCTURE A. TSV Formation and Die Bonding Fig. 1 shows three types of die bonding and two types of TSVs. Under the via-first technology, devices and TSVs are fabricated first, metal layers are deposited, and then dies are bonded. Therefore, TSVs in via-first technology are surrounded 2156-3950/$26.00 © 2011 IEEE