IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002 1335 A Digital-to-Analog Converter Based on Differential-Quad Switching Sungkyung Park, Gyudong Kim, Sin-Chong Park, and Wonchan Kim Abstract—A high-conversion-rate high-resolution oversampling digital-to-analog converter (DAC) for direct digital modulation is addressed in this paper. A new type of switching scheme, called dif- ferential-quad switching, is presented. To verify the feasibility of this scheme, essential parts with some auxiliary circuitry for inter- facing were fabricated in a 0.8- m CMOS technology. Measured results show that the switching scheme provides 11-b resolution at 100 MSamples/s and 6-b at 1 GSamples/s. The degradation in signal-to-noise ratio is not observed for the variation of the supply voltage down to 1.5 V, which means the proposed scheme is suitable for low-voltage applications. Index Terms—Differential-quad switching, digital-to-analog converter, direct digital modulation, oversampling. I. INTRODUCTION I N DIRECT digital modulation systems, the signal is upcon- verted in the digital domain, and the modulated digital signal is converted into a modulated analog form. In these systems, a digital-to-analog converter (DAC) whose conversion rate is more than the Nyquist rate of the carrier frequency and whose resolution is better than that in the baseband is required. Many examples of high-speed high-resolution DACs have been reported in various technologies [1]–[4]. In this paper, a high-resolution high-speed DAC which works in the low-voltage regime is proposed, tailored to direct digital modulation applications. An effective switching scheme, called differential-quad switching (DQS), is proposed for the oversampling DAC to meet the requirements for direct digital modulation. DQS is investigated in Section II. Design consideration and experimental results are given in Sections III and IV, respec- tively, followed by concluding remarks in Section V. II. DIFFERENTIAL-QUAD SWITCHING Practically, it is not possible to design a perfect switch used as a 1-b DAC. Examples of imperfect switching which causes signal-dependent nonlinearity are the asymmetry in the beginning of transition and the finish of transition, the unequal pulsewidth between “1” pulse and “0” pulse, and the asymmetry between rising transient and falling transient. Return-to-zero (RZ) switching can eliminate the distortion from uneven pulse duration for the low-frequency oversampling DAC. However, RZ switching has two major problems. First, in high frequency, if the short pulse (“1” or “0”) cannot switch to the full level, the history effect of the input stream is not elimi- nated and generates data-dependent noise. Therefore, the width Manuscript received August 3, 2000; revised April 7, 2002. S. Park and W. Kim are with the School of Electrical Engineering, Seoul National University, Seoul 151-744, Korea (e-mail: bible@iclab.snu.ac.kr). G. Kim is with Silicon Image Inc., Sunnyvale, CA 94086 USA. S.-C. Park is with the Information and Communications University, Daejeon 305-600, Korea. Publisher Item Identifier 10.1109/JSSC.2002.803056. (a) (b) Fig. 1. (a) Simplified circuit based on DQS. (b) Example waveforms of DQS. of the short pulse that can switch to the full level limits the op- eration frequency of the DAC. Second, power efficiency is low for high-frequency operation because the pulses are returned to a predefined level for every sample. Ordinary differential switching is capable of eliminating many nonlinearities caused by imperfect switching but still has some data-dependent nonlinearity, because the number of transitions for each clock edge varies according to the data pattern. The switch does not toggle every clock transition, and the switching event is inevitably dependent on the data pattern, introducing noise into the signal band. If, however, the switch toggles every clock edge, this noise will not be in the signal band but in the conversion clock frequency, which is twice as high as the carrier band frequency. This switching is DQS. Fig. 1(a) is the simplified circuit based on DQS. It uses four switches for differential switching, and each switching transistor is driven by a signal shown in Fig. 1(b), which is AND gated with one of the complementary clocks and ; hence, either side toggles every clock instant. The output is logically the same with ordinary differential switching. Switching in this manner eliminates the nonlinearity due to uneven pulse duration, as in RZ switching, because every pulse has the same width. There are at least two and only two signal transitions—one rising and one falling—per 0018-9200/02$17.00 © 2002 IEEE