ELECTRONICS LETTERS 24th May 2001 Vol. 37 No. 11 Low-jitter phase-locked loop based on pseudo-differential delay elements Sungkyung Park, Youngdon Choi, Sang-Geun Lee, Yeon-Jae Jung, Sin-Chong Park and Wonchan Kim A phase-locked loop (PLL) that is highly robust to supply/substrate noise is described. A new type of voltage-controlled oscillator (VCO) based on pseudo-differential delay elements is presented. The proposed circuit is implemented using a 0.35 μm CMOS process technology with a 3.3V supply. It generates 16 clock phases at 250MHz, tailored to gigabit link applications. Introduction: In recent years, advances in technology have enabled CMOS link implementation in the Gbit/s range. As data rates increase, data eye opening becomes narrower. The received data and clock there- fore become more susceptible to various noise sources, of which supply and substrate noise are the most dominant. It is important, therefore, to design a PLL that is highly tolerant of supply and substrate noise, ena- bling jitter reduction and correct data strobing. Papers aimed at relieving this noise problem have been written [1, 2]. The cycle jitter ∆Tc and cycle-to-cycle jitter ∆Tcc are proportional to K = |df/dv|, which is the proportionality constant between the frequency variation and supply/ substrate noise [3]. The jitter is thus proportional to the VCO delay vari- ation and PLL period deviation in the presence of supply and substrate noise. In this Letter, a new type of voltage-controlled oscillator (VCO) is presented to facilitate low-jitter operation of a PLL. To validate the effectiveness of the proposed PLL, it is implemented using 0.35 μm CMOS process technology with a 3.3V supply voltage. The multiphase PLL, which is intended for use in 2Gbit/s parallel link applications, oscillates at 250 MHz and comprises eight delay elements to generate 16 phases. Circuit design: A VCO is the most sensitive building block in a PLL as far as supply/substrate noise is concerned. A novel delay element is pro- posed to overcome this noise. A schematic diagram of the delay element is shown in Fig. 1. The delay element is made up of a core circuit and an auxiliary circuit. Ten transistors, M6–M15, constitute the core circuit while the other transistors constitute the auxiliary circuit. The loop filter output node of the PLL is Vcb, and M6–M9 serve as a current mirror controlled by Vcb. One CMOS inverter composed of M10 and M11 and another inverter composed of M12 and M13 are coupled to each other by a positive feedback circuit (M14 and M15). Thus, two single-ended inverters behave like one differential delay element. This pseudo-differ- ential delay element benefits from both single-ended and differential delay elements. Specifically, the single-ended delay elements provide full-swing outputs without the need for additional buffers. The number of delay elements in a multiphase VCO, however, must be the same as that of the required phases. Conventional differential delay elements require ancillary buffers to provide full-swing outputs. The power consumption is therefore higher. The number of differential delay elements, however, is only half that of the required phases in multiphase applications because one delay ele- ment is capable of generating two phases which are 180° apart. The pro- posed delay element provides a full-swing output without the need for an additional output buffer, which is the virtue of single-ended delay elements, and the number of delay elements is only half that of the required phases, which is the virtue of differential delay elements. The power consumption of the VCO is substantially reduced as a result of the benefits explained above. Furthermore, this compact and feasible circuit behaves as a differential circuit, and is thus immune to supply and substrate noise in itself. The auxiliary circuit composed of M1–M5, R1, and R2 is literally an auxiliary part. M2–M5 guarantee persistent oscillation of the VCO in case Vcb increases near Vdd and M6 turns off. Normally, the delay of a full-swing delay element increases by a small amount as the supply voltage increments slightly. To overcome this, M1 and voltage divider R1 and R2 make Vdb less susceptible to supply noise, enabling less delay variation. The operation of M2, M3, M6, and M7 in the linear region enables the use of a delay element in a low-volt- age regime. A 250MHz multiphase PLL was implemented in a 0.35 μm 2P4M CMOS process with 3.3V supply to validate the effectiveness of the proposed circuit and apply it to a gigabit parallel link application. The loop bandwidth was ~3MHz and the damping factor ~1. The phase margin was ~56°, according to Bode plots. The power consumption of the prototype PLL was < 7 mW in total. Experimental results: The control voltage characteristics are plotted in Fig. 2. Fig. 2a shows the measured VCO gain to be ~335MHz/V. The acquisition time of the PLL is < 2 μs, as shown in Fig. 2b. The VCO and PLL jitter characteristics are shown in Fig. 3. The VCO delay variations of the proposed and starved-inverter-type circuits in the presence of sup- ply and substrate noise are shown in Fig. 3a and b. The delay variation Fig. 1 Pseudo-differential delay element with auxiliary circuit Fig. 2 Control voltage characteristics a VCO oscillation frequency against control voltage b Control voltage settling characteristic Fig. 3 VCO and PLL jitter characteristics a VCO delay variations of proposed and conventional circuits under supply disturbances b VCO delay variations of proposed and conventional circuits under sub- strate disturbances – – – – proposed ——— conventional c Period deviations of proposed PLL under supply disturbances d Period deviations of proposed PLL under substrate disturbances