Published: December 20, 2010 r2010 American Chemical Society 523 dx.doi.org/10.1021/nl1033842 | Nano Lett. 2011, 11, 523–528 LETTER pubs.acs.org/NanoLett Large-Scale Graphene Transistors with Enhanced Performance and Reliability Based on Interface Engineering by Phenylsilane Self-Assembled Monolayers Zihong Liu,* Ageeth A. Bol, and Wilfried Haensch IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, United States ABSTRACT: In this letter, we report the dielectric/graphene interface physics and engineering of large-scale, chemical vapor deposited (CVD) graphene transistors by self-assembling a molecular-scale organosilane monolayer onto the dielectric surface. We show that phenyl-alkyl-terminated self-assembled monolayers (SAM) at the dielectric/graphene interface consis- tently improve the graphene device performance and reliability. The extrinsic field-effect mobility of large-scale CVD graphene transistors on the phenyl-SAM engineered dielectric is currently up to 2500 cm 2 /(V s) at room temperature, considerably higher than the counterparts without the SAM. In addition, significant reduction on the bias stress instability and hysteresis is achieved by the SAM-based interface engineering. Further analysis reveals that charge injection from graphene to the dielectric/graphene interface dominates the observed hysteresis behavior. For both graphene transistors with and without SAMs, the bias stress stability, that is, Dirac point shift under bias stress, is well described by the stretched exponential model with its fitting parameters clearly indicating different interface properties. KEYWORDS: Graphene, field-effect transistor (FET), interface engineering, organosilane, self-assembled monolayer (SAM), charge transport, reliability, hysteresis, bias stress, Dirac point shift G raphene, an atomically thin layer of 2D carbon film, has emerged as a promising candidate material for high-speed nanoelectronics due to its extraordinary electrical and optical properties. 1-8 The intrinsic mobility of graphene is predicted to reach 200 ,000 cm 2 /(V s) at room temperature. 9 Among many other applications, the graphene field-effect transistor (FET) is recognized to be a complement to the traditional silicon FET for the next generation of very large scale integration (VLSI) circuits 4,5,7,8 and, particularly, radio frequency (RF) electronics. 10-13 However, graphene transistors fabricated on dielectric substrates, for example, SiO 2 , typically exhibit a field-effect mobility being multiple orders of magnitude lower than the intrinsic graphene mobility. 8,9 Also, unfavorable hysteresis behavior and electrical instability can always be found in these devices. Graphene FET performance and reliability can be dominated by the dielectric/graphene interface, where a variety of scattering and trapping effects have been identified. 9,14-17 In addition to the intrinsic graphene acoustic phonon scattering, Coulomb impurities, surface roughness, and surface polar phonon scatter- ing from the adjacent dielectric can all affect charge transport in the device. These scattering effects become especially pro- nounced for devices operated at room temperature. This is corroborated by the fact that suspended graphene does not suffer from extrinsic scatterings and thus, is ideal for studying intrinsic graphene properties. 18-20 For device applications, non- polar substrates have been suggested to be beneficial, 9,14 yet finding such materials remains a challenge. Recent work using a hydrophobic hexamethyldisilazane layer as the silicon oxide surface modifier, 16 or using single crystal hexagonal boron nitride (h-BN) as the substrate 21 has shown encouraging results. How- ever, they are based on exfoliated graphene flakes, which are unsuitable for large-scale technological application. Also, the interface physics for the graphene transistor performance and reliability still requires further exploration. In this letter, we report the dielectric/graphene interface physics and interface engineering of bottom-gated, large-scale chemical vapor deposited (CVD) graphene transistors by apply- ing molecular phenyl-terminated organosilane self-assembled monolayers (SAM) onto the dielectric surface. CVD graphene is utilized here due to its scalability and manufacturability for large-area device integration. 22-24 We show that the phenyl- alkyl-SAM-based interface engineering consistently improves the CVD graphene FET mobility, hysteresis, and bias stress stability, making it promising for practical application. Through systematic measurements and model fitting for graphene transistors with and without the phenyl-SAM, we clarify the physical mechanisms responsible for the FET mobility, hysteresis, and bias stress behaviors. Figure 1a shows a general bottom-gated graphene transistor structure used for this study. In our experiments, a heavily doped Received: September 24, 2010 Revised: December 11, 2010