MARISCO: A Multi-Core Platform Laysson Oliveira Luz Universidade Federal do Piauí Departamento de Informática e Estatística layssonoliveir4@gmail.com Ivan Saraiva Silva Universidade Federal do Piauí Departamento de Informática e Estatística ivan@ufpi.edu.br Thiago R. B. da Silva Soares Universidade Federal do Piauí Departamento de Informática e Estatística thiagorbss@gmail.com ABSTRACT Multi-core architecture is the natural result of industrial capability development. For decades enhancements in the performance of microprocessors were based on the reduction the transistors size and increasing the clock frequency. These technological evolutions enabled the integration of more and more transistors on a single chip as well as performance improvement without architectural modification. However, the industrial capability to continuously increase the clock frequency has reached its limits. In recent years with the inability to increase over again the clock frequency and the continuous increase in the integration capacity the industry was conducted to engage in the race for developing processors with multiple processing cores. This paper presents the design and implementation of a multi-core embedded processor platform through the integration of general-purpose processors using a crossbar as interconnection subsystems. All the hardware devices used in the multi-core embedded processor were described in VHDL language aiming an FPGA implementation. Categories and Subject Descriptors C.1.2 [Processor Architecture]: Multiple Data Stream Architectures (Multiprocessors) - Array and vector processors, Associative processors, Connection machines, Interconnection architectures, Multiple-instruction-stream, multiple-data-stream processors (MIMD), Parallel processors, Pipeline processors. General Terms Language, Microprocessors, Reconfigurable Architecture, Instructions. Keywords VHDL, RISCO, Microprocessors, Reconfigurable, Architecture. 1. INTRODUCTION In the past decade was observed that the consumer electronic industry has been engaged in a race to increase the integration capability and the frequency of circuits. This race has emerged to meet the growing demand for consumer electronic devices: mobile phones, personal computers, among other high-tech gadgets. As a consequence devices were developed with enhanced functionality and design complexity. High level of integration, small size and low power consumption became the industry's technological goals. Furthermore significant impact as observed in the work designer's team, the time available for conclude a project reduces considerably [1]. The platform concept emerged with the need to develop new methods aiming to solve the problem of reduced time to market and the gap of technology. The technology gap is the difference between the productivity of development teams and integration capacity of the semiconductor industry. The platform-based design methodology applies directly to the development of multiprocessor systems on chip (MP-SoCs). Such systems consist of an integrated set of cores with different processing capacity (general-purpose processors, dedicated cores, DSPs - Digital Signal Processors, memory, interconnection sub- system, among others). Multi-cores are more restrictive examples of MP-SoCs. It consists generally in the integration of processing cores, memory and interconnection sub-system. A platform is frequently defined as an abstraction that hides or simplifies the design details of a system. A MP-SoC platform consist in a library cores, specified at some abstraction level, and delivered with rules of integration and information about performance functionalities. This paper presents the design of a multi-core embedded processor platform. The design uses the RISCO [2] processor, a crossbar as interconnection subsystems and distributed memories. The paper is organized as follows: Section two presents the multi-core embedded platform; section three presents a discussion about integration and validation experiments and section four presents future works. 2. MULTI-CORE WORKS Multi-core architectures have become mainstream in embedded systems design. Currently it is easy to find several papers in major journals and conferences on topics related to multi-core architectures. Many of them focus on topics related to software development: programming, operating systems, virtualization, and so one. Many other address topics related to hardware development, mainly interconnecting sub-systems, low power architectures, and memory hierarchy, among other topics. This section will not present a comparative study between the architecture proposed in this paper and others presented in the literature, that is present architecture as the platform ARM cortex A9 (designed for mobile computation of geral purpose that can be custom before produced)[3] and the architecture Intel Core i7 (also of geral purpose, that use the concept of symmetric multithreading)[4]. The main reason is that it is a work with educational purpose that aims at a first moment to design a platform that after will be used to develop new hardware and software resources to multi-core processors.