Designing efficient QCA logical circuits with power dissipation analysis Shadi Sheikhfaal, Shaahin Angizi n , Soheil Sarmadi, Mohammad Hossein Moaiyeri, Samira Sayedsalehi School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran 1953833511, Iran article info Article history: Received 12 November 2014 Received in revised form 20 February 2015 Accepted 23 March 2015 Keywords: Nanoelectronics Quantum-dot cellular automata Five-input majority gate Power analysis Dissipated power Even parity generator abstract Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our experimentations, we found that these designs suffer from high power consumption and also structural weaknesses. Therefore, a new ultra-low power and low-complexity five-input majority gate is proposed. For examining our presented design in large array of QCA structures even parity generators, as instances of logical circuits with different lengths up to 32 bits are presented. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects. QCADesigner tool is used to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool. & 2015 Elsevier Ltd. All rights reserved. 1. Introduction Shrinkage in feature size of CMOS circuits has become a controversial issue for designers to implement a circuit with low power consumption besides considerable decreasing in the size. Therefore, the necessity for an alternative technology which could offer revolutionary approach for working at Nano-scale was seemed more vital than ever [1]. Accordingly, Quantum-dot Cellular Automata (QCA) is presented which can perform with ultra-low power despite its high performance. The basic unit in this technology is a cell which consists of four dots and two excess electrons and all the logic gates and circuits can be made based on it. The computation in an array of QCA cells is performed through Coulombic interaction [2]. According to the considerable advances in semiconductor materials used in a existing CMOS fabrication process, semiconductor implementation of QCA is so promising. The type of used technology in this paper is semiconductor QCA which is composed of four quantum-dots manufactured by semi- conductive materials [3]. Since there is no electrical current in QCA computations, the power consumption is considerably lower than conventional CMOS circuits. Nevertheless, it is necessary to characterize all aspects of a new technology, so several studies have been performed in the area of QCA power [4–8]. One of the most accurate power dissipation models has been proposed by Timler and Lent [4] and an upper bound power dissipation for QCA circuits is estimated by Srivastava et al. [6] based on it. Further- more, in recent years, lots of investigations have been launched in order to design various digital circuits based on this technology; new designs for five-input majority gate [10–13,27,28], structures for one-bit full-adder cell [10,11,21,22], designs for flip-flops and memory cells [14,15,23], QCA complex gate designs [29,32] and also studies on reversible circuits [24,25] have been presented. There are three main obstacles for exploiting complete poten- tial of QCA circuits as is thoroughly discussed in [36]. The first and the most important problem is the realization of QCA circuits capable of processing at room temperature, however Nanomagnet based QCA circuits can be realized in mentioned temperature but with higher dimensions [37]. The second issue is the means by which the output or input cells could be fixed and measured. The third issue is circuit tolerance to possible fabrication faults. The mentioned obstacles motivated further studies in future. The main aim of our work is to analyze the power dissipation for proposing efficient QCA logical circuits. In the first step, a comprehensible study over power and structural subjects of the previously proposed five-input majority gates is made. To modify the structural weaknesses and reduce the power dissipation in the mentioned circuits, an ultra-low power and optimal five-input majority gate is proposed. In the second step, new even parity generators (up to 32-bit) as the instances of logical circuits are designed by employing the proposed gate. A detailed analysis on the power consumption of the presented logical circuits and the best reported ones in literatures is performed. Finally, considering Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2015.03.016 0026-2692/& 2015 Elsevier Ltd. All rights reserved. n Corresponding author. Tel.: þ98 9127238731. E-mail addresses: sh_sheikhfaal@ymail.com (S. Sheikhfaal), sh.angizi@ipm.ir (S. Angizi), s-sarmadi@iau-arak.ac.ir (S. Sarmadi), s_sayedsalehi@azad.ac.ir (S. Sayedsalehi). Microelectronics Journal 46 (2015) 462–471