311 Bharat Choudhary, International Journal of Electronics, Electrical and Computational System IJEECS ISSN 2348-117X Volume 4, Special Issue March 2015 New design of Exclusive-OR (XOR) gate by using low-power MCML tri-state buffer Bharat Choudhary * * Dept. of ECE, Delhi Technological University (Formerly Delhi College of Engineering), Delhi, 110042, ABSTRACT This paper presents a new technique to implement exclusive-OR (XOR) gate by using MOS current mode logic (MCML) low-power tri-state buffer concept. The design of the proposed MCML XOR gate is carried out through analytical modeling of its static parameters. The proposed MCML XOR gate is analyzed and the performance is compared with the traditional MCML XOR gate. The theoretical propositions are validated through SPICE simulations using TSMC 0.18mm CMOS technology parameters. Keywords- MCML, Exclusive-OR (XOR) gate, Tri-state circuit, Low-power. 1. Introduction The development of high-speed circuits have two major requirements one is higher levels of integration to provide higher performance at low cost design and second is to provide low-power system-on-chip implementations by using popular VLSI technologies such as CMOS. Although the performance of CMOS technologies improves notably with shrinking of technology, but conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of various applications. Conventional CMOS logic style is not preferred as it also generates large switching noise and consumes power depending on the operating frequency. Among the possible logic styles, one of the most successful logic style is the Source-coupled logic (SCL). It has only static power consumption and allows a switching noise reduction by two orders of magnitude compared to conventional CMOS logic style [1-4]. MOS Current Mode Logic (MCML) is a substitute differential logic style based on current steering logic [5], consequently capable of allowing high speed designs. Fundamentally, a constant current is forced through complementing logic branches between ground and supply voltage lines. This current is alternated between the branches on application of differential signals to them. In addition to elimination of enormous switching noise, this logic style consumes less power in conventional CMOS static logic, although static power consumption is observed irrespectively. Therefore, MCML circuits are useful for low- power, high-speed, high performance and mixed-signal applications. The paper is organized in five sections including the introductory one in first section. In second section MCML circuit is briefly reviewed and traditional design of exclusive-OR (XOR) gate is discussed using series-gating approach followed by introduction of tri-state buffer circuits and design method of exclusive-OR gate with the help of MCML tri-state buffer in section 3. In section 4, exclusive-OR (XOR) gate implementation and the functional verification is carried out through various simulations. The paper is concluded in final section 5.