IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 2, APRIL 2009 47 Diplexer Design Implementing Highly Miniaturized Multilayer Superconducting Hybrids and Filters Paul D. Laforge, Member, IEEE, Raafat R. Mansour, Fellow, IEEE, and Ming Yu, Fellow, IEEE Abstract—Multilayer superconducting quadrature hybrids for diplexer applications are reported for the first time in this paper. The hybrids employ highly miniature lumped element components embedded within four metal layers. The thin dielectric layers be- tween the metal layers and the small feature size of the process allow for the miniaturization of lumped element capacitors and in- ductors. Hybrid-coupled diplexers using lumped element hybrids and filters have been developed, fabricated, and tested. A novel filter configuration that employs inter-resonator tap connections is also demonstrated for implementation in wideband filter appli- cations. The whole integrated high (quality factor) diplexer is highly miniaturized being approximately in size at a fre- quency of 1.0 GHz. The diplexer structures are amenable to su- perconductor microelectronics technology and can be integrated monolithically with a superconducting receiver on a single chip. Index Terms—Bandpass filters, diplexers, niobium, radio re- ceivers, superconducting filters. I. INTRODUCTION S UPERCONDUCTOR microelectronics (SME) technology has the potential for the realization of highly advanced pro- grammable software radios. SME circuits can manage digital signals with clock speeds of 40 GHz. These high clock speeds also allow for a digital-radio-frequency (RF) architecture with direct conversion up to 10–12 GHz [1]. RF filters are key com- ponents in the front end of the superconducting digital receiver. Fig. 1 shows the architecture for the receiver of an SME radio. The RF signal received by the antenna passes through an RF filter and is sent to an ultralow noise bandpass analog-to-digital (ADC) converter. This architecture eliminates the need for the down conversion of the RF signal using a mixer and a local oscil- lator. The down conversion process is entirely digital, including the local oscillator. The digital signal is then conditioned at ul- trafast speeds creating a true software radio. An RF channelizer, which replaces the RF filter shown in Fig. 1, can improve the performance of the SME receiver. There Manuscript received September 08, 2008; revised December 12, 2008. First published February 03, 2009; current version published April 01, 2009. This paper was recommended by Associate Editor O. Mukhanov. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC) and COM DEV Ltd. P. D. Laforge is with the University of Regina, Regina, SK, S4S 0A2, Canada (e-mail: Paul.Laforge@uregina.ca). R. R. Mansour is with the University of Waterloo, Waterloo, ON, N2L 3G1, Canada (e-mail: rmansour@maxwell.uwaterloo.ca). M. Yu is with COM DEV International, Cambridge, ON, N1R 7H6, Canada (e-mail: ming.yu@comdev.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TASC.2009.2012433 Fig. 1. Architecture of the receiver of an SME radio. exists a tradeoff between the bandwidth and the dynamic range of the superconducting ADC [2]. The RF channelizer can also reject unwanted signals between narrow sub-bands. The dy- namic range and the spur-free dynamic range of the receiver determine whether it can deal with these unwanted signals [2]. Also, for larger bandwidths at higher frequencies, the total noise is increased which decreases the dynamic range. For these wide- band applications, an RF channelizer can better manage wide- band signals comprised of narrow sub-bands. The proposed baseline design of the architecture shown in Fig. 1 uses high (quality factor) room-temperature filters. The availability of miniature superconducting microwave com- ponents will make it possible to integrate an RF channelizer and the receiver on a single chip. The design and fabrication of multilayer superconducting quadrature hybrids is presented for the first time in this paper. A diplexer using the hybrid-coupled diplexer architecture shown in Fig. 2 is implemented using this multilayer process. The two channels of the diplexer have been designed with center frequencies of 1.0 and 1.15 GHz. A hybrid is designed at each of these center frequencies. The hybrid designed at 1.0 GHz has a more compact spiral inductor than the hybrid designed at a center frequency of 1.15 GHz. A channelizer comprised of two identical filters and two identical hybrids is designed for each of the two channels. A filter designed at the center frequency of the additional channel is placed at the output of the channelizer to demonstrate its application as a diplexer. One diplexer has GHz and GHz, as shown in Fig. 2, and the other diplexer has GHz and GHz. Because the two channels are near each other in frequency, both of these diplexer options perform well due to the bandwidth of the hybrids. The filter and hybrids are designed with the benefit of high capacitance parallel plate capacitors and compact spiral inductors allowed by the fabrication process. The diplexers are highly miniaturized with very low loss. 1051-8223/$25.00 © 2009 IEEE Authorized licensed use limited to: University of Waterloo. Downloaded on April 18, 2009 at 11:55 from IEEE Xplore. Restrictions apply.