A SUBSTRATE ISOLATED LDO FOR AN INDUCTIVELY POWERED RETINAL IMPLANT C. Brendler 1 , N. Pour Aryan 1 , V. Rieger 1 , S. Klinger 2 and A. Rothermel 1 1 Institute of Microelectronics, University of Ulm, Germany 2 Retina Implant AG, Reutlingen, Germany christian.brendler@uni-ulm.de Abstract: A substrate isolated LDO for an inductively pow- ered retinal implant to generate a negative substrate volt- age of -2V out of a more negative rectified voltage down to -7V is presented. Due to the fact that the negative recti- fied input voltage is negative relative to substrate, the LDO has to be completely isolated against substrate. The LDO has an Open Loop Gain of 66dB and a PSRR of -81dB at low frequencies. The process used is a 350nm High Voltage BiCMOS technology. Keywords: Isolated LDO, substrate generation, SoC, in- ductively powered, biomedical implant Introduction Almost in all types of biomedical implants like retinal im- plants or pacemakers, supplying power to the electronic de- vice is a challenge. Powering the implants is possible by using batteries or percutaneous lead wires. These require additional surgical operations for battery exchange or pose the risk of infection. To avoid these drawbacks many biomedical implants are powered inductively through the skin [1]. Power regulation is necessary due to coupling variations. The on-chip supply voltages have to be generated out of the rectified voltages with voltage regulators like Low Drop Out (LDO) regula- tors [2]. The drawback of state of the art LDOs is that the substrate has to be at the lowest potential on the ASIC [3]. The proposed isolated LDO generates the negative substrate voltage V SS (-2V). Figure 1 shows the architecture of the system. The inductively generated HF is rectified with two half wave rectifiers into a positive and negative rectified voltage. External capacitors are needed to buffer high cur- rent pulses. The band gap circuit (BG) generates the refer- ence voltage Vref for the two error amplifiers and is sup- plied by the positive rectified voltage. The output of both LDOs are fed back to the error amplifiers. As the positive LDO that generates V DD (+2V ) is state of the art it will not be further investigated. The isolated negative LDO generates the negative substrate potential of -2V . That means it has to be stable to substrate potential variations. Additionally the input of the LDO is more negative with respect to substrate and has to be com- pletely isolated from substrate. To our knowledge no other LDO working below the sub- strate voltage potential exists in open literature. Inductive coupling BG pos. rectified neg. rectified VDD +2V VSS -2V P-substrate of ASIC Potential negative to P-substrate Figure 1: system architecture Methods The isolated LDO proposed in this work (Figure 2) has a rectified input voltage that is more negative than the sub- strate and has to generate the substrate voltage on the out- put. Because of this negative input voltage against substrate there has to be an isolation from the substrate. Input voltage to substrate isolation No PN-junction between negative input and p-substrate is allowed to conduct. Therefore isolated NMOS transistors ("MNiso1" to "MNiso4", Figure 2) have to be used. In the used technology High Voltage (HV) transistors with work- ing ranges up to 50V are available. But these so called HV isolated NMOS transistors are not completely isolated (Fig- ure 3). Only the source is isolated by an N-well that has the potential of the drain and therewith the drain has to be pos- itive against the p-substrate. MN iso 1 MN iso 2 MN iso 3 MN iso 4 V_ref VDD Bias from BG MP 3 MP 1 MP 2 MP 4 MP 5 positive rectified R1 R2 C MN iso 5 Neg. rectified voltage negative to p-substrate VSS -2V P-substrate of ASIC Figure 2: Schematic of isolated negative LDO Biomed Tech 2013; 58 (Suppl. 1) © 2013 by Walter de Gruyter · Berlin · Boston. DOI 10.1515/bmt-2013-4367 Unauthenticated Download Date | 3/9/18 2:15 PM