Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi and Koji Yamazaki Dept. of Computer Science, Meiji University Higashimita, Tama-ku, Kawasaki 214-8571, Japan E-mail: {yamada, kotake, h-taka, yamaz}@cs.meiji.ac.jp Abstract We present a technique for identifying redundan- t crosspoint faults in sequential PLAs with fault-free hardware reset. This technique can find most redundant crosspoint faults efficiently. Experimental results show that about 7% of crosspoint faults are redundant on an average in the sequential PLAs synthesized by a com- mercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks. 1. Introduction Identification of untestable and redundant faults in sequential circuits is of great importance to speed up test generation, to reduce circuit size, to improve testa- bility, etc.[1, 2]. Therefore various methods of identify- ing untestable and redundant stuck-at faults in sequen- tial circuits composed of gates and flip-flops have been proposed [3]-[11]. All untestable faults can be found by checking whether the state diagrams of the fault-free and faulty circuits are different from each other [5, 6]. However, this method cannot handle large circuits due to waste of computing resources. Techniques for iden- tifying untestable faults from the illegal combination of logic values in the circuit [8, 9] or unreachable states of the circuit [10, 11] may not find all untestable faults, although they are possibly applicable for large circuits. PLAs have been used to realize microprograms, con- trollers, etc. in the microprocessors because they are easy to design and implement. Recently the use of CPLDs composed of many small PLA blocks is increas- ing to realize system VLSIs in the field [12, 13]. PLAs inherently contain many redundant crosspoint faults. For combinational PLAs, literatures [14, 15, 16] have discussed about how many crosspoint faults are redun- dant, and possibility of removing more than one redun- dant crosspoint fault without changing the behavior of a given circuit, etc. However, no research has been done for sequential PLAs. This paper proposes an efficient technique for iden- tifying redundant crosspoint faults in sequential PLAs with fault-free hardware reset and evaluates the per- centage of redundant crosspoint faults using the se- quential PLAs synthesized by a commercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks. 2. Testing of PLAs [14][15] A PLA consists of the input decoders, AND array, and OR array, that realizes logic functions in the sum- of-products form. An example of PLA is shown in Fig.1. In Fig.1(b), 0’s denote the presence of AND- devices at the crosspoints of the product lines and the bit lines, and 1’s denote the presence of OR-devices at the crosspoints of the product lines and the output lines. Therefore product lines 1, 2 and 3 of this PLA re- alize the product terms x 1 x 2 x 3 , x 1 x 2 and x 2 x 3 respec- tively, and the output functions are f 1 = x 1 x 2 x 3 +x 1 x 2 and f 2 = x 1 x 2 + x 2 x 3 . For the crosspoint-oriented test generation, we usu- ally assume single extra-device fault or missing-device fault in the AND or OR array. Under this assumption, consider crosspoint faults on product line 3 of Fig.1(a). Input vector x 1 x 2 x 3 = 110 can activate extra AND- device faults at (3, 2), (3, 4) and (3, 5), where (i, j ) denotes the crosspoint of a product line i and a bit line j . This means that these faults cause a zero-error (1 → 0) on product line 3 for the application of this input vector. Then this zero-error will propagate to output line 8 to be detected. An extra OR-device fault at (3, 7) and a missing OR-device fault at (3, 8) on product line 3 are also activated and detected by this input vector. On the other hand, we need input vector