ELECTRICAL THROUGH WAFER INTERCONNECTS WITH 0.05 PICO FARADS PARASITIC CAPACITANCE ON 400 μM THICK SILICON SUBSTRATE Ching H. Cheng, Arif S. Ergun, and Butrus T. Khuri-Yakub Edward L. Ginzton Laboratory, Stanford University Stanford, CA 94305-4085 ABSTRACT This paper presents a technology for high density and low parasitic capacitance electrical through-wafer interconnects (vias) to an array of micromachined transducers on a silicon wafer. Vertical wafer feedthroughs (interconnects) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. A 20 to 1 high aspect ratio 400 μm long and 20 μm diameter interconnect is achieved by using deep reactive ion etching (DRIE). Reduction of the parasitic capacitance to the substrate is achieved using reverse-biased pn- junction diodes operating in the depletion region. A parasitic capacitance of 0.05 pF has been demonstrated by this approach. This three-dimensional architecture allows for elegant wafer-level packaging through simple flip-chip bonding of the chip’s backside to a printed circuit board (PCB) or a signal processing wafer. INTRODUCTION In micro-electro-mechanical-systems (MEMS) applications, it is advantageous to have electronic circuitry as near the sensor/actuator as possible. However, integrating both the MEMS devices with electronics on the same wafer often leads to a compromise between the performance of either or both systems. An excellent solution to this problem is to construct the optimum MEMS devices and electronics on separate wafers, provide a through wafer interconnect with minimum resistance and capacitance on the MEMS wafer, then flip-chip bond the two wafers (Fig. 1). In this fashion, the MEMS wafer can be fully populated such as in applications of infra-red (IR) focal plane arrays or three-dimensional ultrasound imaging [1-5]. Finally, since the MEMS and electronics wafers can be fabricated in different facilities, the overall yield of the manufacturing process is enhanced. Printed Circuit Board Integrated Circuits Wire Bonding Solder Bumps Through Wafer Interconnects MEMS Devices Figure 1. Packaging schematic of through-wafer interconnects. The architecture of achieving this hybrid integration with high density is based on through-wafer vertical interconnects with high aspect ratio. Many processes have been previously used to fabricate through-wafer interconnects [6][7] including dry etched polysilicon filled interconnects by Chow et al [8]. In previous work, we integrated similar interconnects into an active sensor arrays and made improvements on parasitic capacitance from 2 pF to 0.28 pF [1]. To further reduce the parasitic capacitance, we propose to use a through wafer interconnect as shown in Fig. 2. The interconnect presents a parallel capacitance and a series resistance to the input impedance of the MEMS device. Thus, for operation that is not limited by the interconnect, both the capacitance and resistance have to be very small. We will present a technology where the parasitic capacitance is reduced to 0.05 pF in a silicon wafer that is 400 μm thick with a resistivity of 1000 Ω-cm and with a via that has a diameter of 20 μm. PN Junction Front Side Pad PN Junction Through-Wafer Interconnect PN Junction Backside Pad Ohmic Contact Solder Pad Ground Strip Line Silicon Substrate Polysilicon Sealed Front Side Devices Image Processing Chip Solder Bump Figure 2. Schematic of the through-wafer interconnect. For our current application, the through-wafer interconnect is used for integration of two-dimensional ultrasonic transducer arrays with electronic dies. In an ultrasonic transducer array operation, the parasitic capacitance of the interconnect between an array element and its transmit/receive electronics is the limiting factor for the dynamic range and bandwidth. Therefore, it is always best to put the electronics as close to the array elements as possible. In this work, we demonstrate a method to integrate a 128 x 128 capacitive micromachined ultrasonic transducer (CMUT) array with the electronic circuit without sacrificing the performance of either while minimizing the parasitic capacitance. To do this, an electrical through-wafer interconnect is employed to address the array elements individually, where the front side of the wafer is fully populated with the ultrasonic array elements, and the backside is solely dedicated to bond pads for the flip-chip bonding to the printed circuit board (PCB) or the integrated circuits (Fig. 1). In this manner, the parasitics due to any interconnection cable are avoided. To further improve the device performance, the parasitic capacitance of the through-wafer interconnects to the silicon substrate needs to be reduced to a much lower level than the device capacitance. Travel support has been generously provided by the Transducers Research Foundation and by the DARPA MEMS and DARPA bioFlips Programs. 0-9640024-4-2/hh2002/$20©2002TRF DOI 10.31438/trf.hh2002.40 157 Solid-State Sensors, Actuators, and Microsystems Workshop Hilton Head Island, South Carolina, June 2-6, 2002