Vol.:(0123456789) 1 3 Journal of Computational Electronics https://doi.org/10.1007/s10825-019-01362-y Dual‑chirality GAA‑CNTFET‑based SCPF‑TCAM cell design for low power and high performance S. V. V. Satyanarayana 1  · Singh Rohitkumar Shailendra 1  · V. N. Ramakrishnan 1  · Sridevi Sriadibhatla 1 © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube feld-efect transistor (CNTFET)-based self- controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for diferent parameter values with the Stan- ford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a signifcant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP. Keywords Delay · Diameter · GAA CNTFET · Low power · Match/miss · SCPF · TCAM 1 Introduction According to the recommendations of the International Technology Roadmap for Semiconductors (ITRS), there is a substantial need for transistors with channel length of less than 32 nm [1]. However, below 32 nm, metal oxide semiconductor (MOS) technology sufers from high leak- age currents, mobility degradation, and threshold voltage instability, as well as becoming sensitive to process–volt- age–time (PVT) variations [2, 3]. To address these issues at the nanoscale, an alternative to MOS transistors must therefore be pursued. Devices such as fn-based feld-efect transistors (FinFETs) driven by Intel, fully depleted silicon- on-insulator (FD-SOI) technology led by ST Microelectron- ics, carbon nanotube feld-efect transistors (CNTFETs) lead by IBM, as well as the resonant tunnelling diode (RTD) and single-electron transistor (SET) are some of devices that have been introduced to replace complementary (C)MOS transistors. The CNTFET is one of the promising candidates for application beyond the 32-nm node due to its properties such as high mobility via ballistic transport, high mechanical and thermal stability, high resistance to electromigration, high transconductance, superior subthreshold slope, superior threshold voltage, high current density, high I ON /I OFF ratio, high switching reliability, high-temperature resistance, and strong covalent bonding [4, 5]. This paper presents a compact circuit-compatible model for the intrinsic channel region of the CNTFET. The mod- eling approach and methodology described in this paper are generally applicable to any one-dimensional (1-D) device. This model is valid for a wide range of CNTFETs with chi- rality and diameter varying from 0.2 to 2 nm, with either semiconductor or metallic nature. This model includes the quantum confnement efects in both the axial and circum- ferential directions. To make it compatible with digital and analog applications, a dynamic gate capacitance net- work is implemented to describe the real-time dynamic response. The model includes channel elastic scattering, the doped source/drain region, the Schottky barrier resist- ance, multiple CNTs per device, and other devices/circuits. The GAA CNTFET model used in the simulation is based on the SPICE-compatible Verilog-A model developed by Stanford University. In particular, the model describes an enhancement-mode MOSFET device with carbon nanotubes * S. V. V. Satyanarayana svvsatyanarayana8589@gmail.com Singh Rohitkumar Shailendra gudiyarohit2417@gmail.com 1 VIT University, Vellore 632014, India