1592 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012 Effectiveness of Stressors in Aggressively Scaled FinFETs Nuo Xu, Student Member, IEEE, Byron Ho, Student Member, IEEE, Munkang Choi, Victor Moroz, and Tsu-Jae King Liu, Fellow, IEEE Abstract—The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggres- sively scaled FinFETs are studied for different stressor technolo- gies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is 1.5× larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the chan- nel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected. Index Terms—Carrier mobility, contact etch-stop layer (CESL), FinFET, gate first, gate last, Si:C, SiGe, source/drain (S/D) stres- sors, strain, stress transfer efficiency (STE). I. I NTRODUCTION T HREE-dimensional transistor structures such as double- gate FinFET [1], [2] and trigate [3], [4] FET are slated for adoption in sub-22-nm CMOS technology nodes due to their superior electrostatic integrity as compared to the conventional planar bulk MOSFET [5]–[8]. Recent experimental results show that the FinFET performs well even when the fin width is reduced to ∼4 nm to enable gate length (L g ) scaling down to 10 nm [8]. Since strained-silicon technology is now used in volume production to enhance the performance of planar bulk CMOS devices [9], it is important to examine how this technology should be adapted to 3-D transistor structures to achieve the best possible performance. Previous studies have shown that process-induced stress can boost FinFET performance, but these either assumed ideal uniaxial stress [10] or did not fully comprehend the impact of technology choices (e.g., starting substrate material and gate-stack formation process) and con- tinued transistor scaling [11], [12]. This paper presents a comprehensive simulation-based study of stress in FinFET structures induced by a strained contact etch-stop layer (CESL) or strained-source/drain (S/D) stressors, which com- pares results for bulk-silicon versus silicon-on-insulator (SOI) Manuscript received December 25, 2011; revised February 27, 2012; ac- cepted February 28, 2012. Date of publication April 4, 2012; date of current version May 23, 2012. This work was supported by the UC Discovery Grant ele07-10283 under the IMPACT Program. The review of this paper was arranged by Editor H. Jaouen. N. Xu, B. Ho, and T.-J. K. Liu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: nuoxu@eecs.berkeley.edu). M. Choi and V. Moroz are with Synopsys Inc., Mountain View, CA 94043 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2189861 Fig. 1. Schematic plan view of FinFETs and region simulated in this work. substrates and gate-first versus gate-last process integration schemes. The impact of the stressors on the effective carrier mobility is presented to evaluate their efficacy for boosting FinFET performance, down to sub-10-nm L g . II. STE IN ADVANCED FINFETS A. Simulation Methodology The process simulator within the Sentaurus technology computer-aided-design software suite [13], which uses the finite-element method, was used to perform 3-D simulations of stress within FinFETs with (100) top and (110) sidewall surfaces and [110] channel direction. Temperature-dependent strain relaxation time and anisotropy of mechanical properties are taken into account. Fig. 1 shows a schematic plan view of nested FinFET devices, which indicates the region simulated in this work. Two kinds of stressors are considered herein (+1-GPa initial stress): a strained CESL and strained S/D regions (carbon-doped silicon, Si:C, for n-channel devices and silicon– germanium alloy, Si 1−x Ge x , for p-channel devices). The CESL is formed by depositing an amorphous silicon nitride layer at ambient temperature, after gate-stack and S/D formation [14]. Selective Si:C or Si 1−x Ge x epitaxial growth with a temperature of 800 K is used to form the strained S/D regions for n- or p-channel FinFETs, respectively, to induce longitudinal stress and boost effective mobility [15]–[17]. For SOI FinFETs, the fin S/D regions are not etched away prior to the selective epitaxy, i.e., the strained S/D regions wrap around the fin S/D regions so that only a portion of the S/D regions is strained, as shown in Fig. 2(a). For bulk FinFETs, the fin S/D regions are assumed to be etched away prior to the selective epitaxy, since the bulk-silicon substrate provides a template for epitaxial growth, so that the entire S/D regions are strained [18], [19], as shown in Fig. 2(b). (This represents the best case scenario; 0018-9383/$31.00 © 2012 IEEE