144 IEEE TRANSACTIONS ONPOWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013 Phase-Locked Loop Based on Selective Harmonics Elimination for Utility Applications Naji Rajai Nasri Ama, Fernando Ortiz Martinz, Lourenc ¸o Matakas, Jr., and Fuad Kassab Junior, Member, IEEE Abstract—Phase-locked loops (PLL) are widely used in power electronics equipment connected to the mains. The use of a square wave voltage-controlled oscillator instead of a sinusoidal one elim- inates one multiplier, resulting in a simple PLL algorithm, suitable for low-cost processors. In spite of its simplicity, distorted grid voltages cause steady-state phase error. This paper proposes the use of a modified square waveform obtained by the selective har- monics elimination (SHE) method to solve the phase error prob- lem. Simulation and experimental results for the steady state and the transient tests are presented to validate the proposed single- phase and three-phase SHE-PLL methods. The tests using a field- programmable gate array show that the dynamic response of the proposed method is similar to that of classical PLL, with a simpler implementation. Index Terms—Field-programmable gate arrays (FPGA), phase- locked loops (PLL), power electronics. I. INTRODUCTION P HASE-LOCKED loops (PLLs) are widely used in commu- nication, control, automation, and instrumentation systems to achieve signal synchronization. Recently, PLLs have found many applications in grid-connected power electronic devices: 1) to synchronize thyristor firing circuits [1]; 2) to transform variables between stationary and synchronous rotating refer- ence frames [2], [3]; 3) to compute power system disturbances in power quality monitoring systems [4], [5]; and 4) to calculate reference signals for the internal control loops in uninterruptible power supplies [6], dynamic voltage restorers [2], [5], active fil- ters [5], and power converters used in distributed energy systems [3], [7], including wind and photovoltaic systems [8]. In these applications, the PLL detects the phase angle and frequency of the grid fundamental voltage. On the other hand, three-phase PLLs detect the positive sequence component, even for distorted and unbalanced grids [3], [9]–[20]. The typical PLL [21], [22] is composed of a phase detec- tor (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO) (see Fig. 1). Manuscript received September 16, 2011; revised December 6, 2011, February 16, 2012, and March 26, 2012; accepted April 8, 2012. Date of current version September 11, 2012. This work was supported in part by the Sao Paulo Research Foundation (FAPESP) and by the Coordination for the Improvement of Higher Education Personnel (CAPES). The work of N. Ama was supported by a CAPES Grant Scholarship. Recommended for publication by Associate Editor V. Agarwal. The authors are with the Polytechnic School of the University of S˜ ao Paulo, 05508-900 S˜ ao Paulo, Brazil (e-mail; naji@usp.br; fernando_martinz@yahoo.com; matakas@pea.usp.br; fuad@lac.usp.br). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2012.2195506 Fig. 1. PLL—general structure. Fig. 2. Classical single-phase PLL. The PD compares the reference signal v i with the feedback signal v o , producing a signal v f that depends on the phase error between v i and v o . All the cases discussed in this paper use the linearized multiplier type PD [20]–[22] followed by a low- pass filter (LPF). The LF attenuates the oscillating terms of the error signal v f . The VCO generates an output signal v o with frequency ω. The complete system produces an output signal v o , synchronized in phase and frequency with the reference signal v i . Often the feedback signal v o is a unit amplitude sinusoidal signal [1]–[11], [23], [24]. This strategy is defined in this paper as a classical PLL. In [21] and [22], the sinusoidal VCO was replaced by a square wave VCO for analog implementation. This method does not need an analog multiplier in the PD block and is suitable for hardware implementations with pure sinusoidal input. The prod- uct of v i by a two-level (±1) signal v o was accomplished by mixed analog/digital circuitry. Nowadays, the square wave strat- egy can be useful for PLLs implemented in microcontrollers, DSPs, and field-programmable gate arrays (FPGA). In this pa- per, the PD in Fig. 2 that computes the product v mult = v o · v i in the classical PLL is replaced by the operation v mult = sign(v o ), eliminating one multiplier. Another advantage compared to the classical PLL is to reduce memory usage associated with long lookup tables required to store the sinusoidal waveforms with reasonable accuracy. According to [22], the square wave PLL is not applicable to input signals with harmonics, because the steady-state phase error is not null. We propose an improvement on the square wave PLL which consists in substituting the original square wave by the selective harmonics elimination (SHE) waveform, thus minimizing the PLL phase angle error. 0885-8993/$31.00 © 2012 IEEE