Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits S. Strangio a,⇑ , P. Palestri a , M. Lanuzza b , D. Esseni a , F. Crupi b , L. Selmi a a DPIA, Università degli Studi di Udine, Via delle Scienze 206, 33100 Udine, Italy b DIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy article info Article history: Available online xxxx The review of this paper was arranged by Viktor Sverdlov Keywords: III-V TFET Full adders Ripple carry adders abstract In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topolo- gies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solu- tion. The extracted delays and energy characteristics are post-processed and translated into figures-of- merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full- adder topology) are presented and discussed. Ó 2016 Elsevier Ltd. All rights reserved. 1. Introduction The sub-threshold swing (SS) represents the key device param- eter to improve the energy efficiency of digital circuits. Among var- ious device proposals for future low power applications, the tunnel field-effect-transistor (TFET) beat the conventional MOSFET and is considered as promising solution to achieve sub-60 mV/dec opera- tion at 300 K in standard CMOS compatible processes [1–13]. Therefore, many efforts are being devoted to the fabrication of TFETs with high performance electrical characteristics [1–5]. In this context, full-quantum simulators [6–8] are widely used as modeling tools to guide the design of such innovative devices, whereas mixed device/circuit simulations are exploited for early analysis at circuit level [9–13]. A virtual III-V TFET technology plat- form has been recently proposed by Baravelli et al. based on 3D full-quantum simulations [7,8]. An early benchmark against a future CMOS FinFET platform [14,15], based on single device and inverter operation, has been shown [8]. In particular, since the full quantum modeling approach used in [8] does not allow to perform circuit simulations, the inverter operation and the related figures- of-merit (e.g. voltage transfer characteristics - VTC -, V OUT /V IN gain, intrinsic rise and fall times, etc.) have been estimated (i.e. consid- ering the device drain current characteristics and assuming equiv- alent effective capacitive loads instead of the intrinsic device capacitance characteristics). The purpose of the present paper is to extend such a bench- mark, by considering various 24T and 28T full-adders (FA) blocks as vehicle circuits. Figures-of-merit such as delay and average energy per cycle are extracted and discussed for both TFET and CMOS FinFET implementations. The present paper is an extended version of the work presented at EUROSOI-ULIS 2016 Conference [13], where only preliminary results on the standard 28T full- adder topology were discussed. 2. Simulation methodology Fig. 1 sketches the device structures considered in this work, which are: (1) the complementary square cross-section InAs/ AlGaSb TFET nanowires proposed in [8]; (2) the 10-nm node CMOS FinFETs described in [14]. Our analysis uses a multi-scale simulation approach, ranging from device simulations to circuit simulations. As regards the TFETs, the TCAD simulator Sentaurus SDEVICE [16] has been cali- brated to reproduce the full-quantum simulation of the AlGaSb/ InAs hetero-structure [7,8]. At the circuit level, the look-up table (LUT) compact models implemented in Verilog-A enabled time- efficient simulations. As regards the CMOS FinFETs, we used the Predictive-Technology-Models of Multi-Gate transistors (PTM- MG) projected to the 10-nm node available at [15]. http://dx.doi.org/10.1016/j.sse.2016.10.022 0038-1101/Ó 2016 Elsevier Ltd. All rights reserved. ⇑ Corresponding author. E-mail address: seb88str@gmail.com (S. Strangio). Solid-State Electronics xxx (2016) xxx–xxx Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse Please cite this article in press as: Strangio S et al. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node con- sidering basic arithmentic circuits. Solid State Electron (2016), http://dx.doi.org/10.1016/j.sse.2016.10.022