Simulation comparison of InGaP/GaAs HBT thermal performance in wire-bonding and ip-chip technologies Vincenzo d'Alessandro a, , Antonio Pio Catalano a , Alessandro Magnani a , Lorenzo Codecasa b , Niccolò Rinaldi a , Brian Moser c , Peter J. Zampardi d a Department of Electrical Engineering and Information Technology, University Federico II, Naples, Italy b Department of Electronics, Information, and Bioengineering, Politecnico di Milano, Milan, Italy c Qorvo, Inc., Thorndike Rd., Greensboro, NC, USA d Qorvo, Inc., Newbury Park, CA, USA abstract article info Article history: Received 2 June 2017 Received in revised form 7 September 2017 Accepted 10 September 2017 Available online xxxx This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs for handset ap- plications in a laminate (package) environment. Both wire-bonding and ip-chip technologies are examined. The combination between an accurate, yet fast, simulation capability and the Design of Experiments technique is employed to quantify the impact of all the key technology parameters and explore a wide range of operating conditions. © 2017 Elsevier Ltd. All rights reserved. Keywords: Design of Experiments (DOE) Finite-element method (FEM) Flip-chip (FC) Gallium arsenide (GaAs) Heterojunction bipolar transistor (HBT) Laminate technology Thermal resistance Wire-bonding (WB) 1. Introduction Gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs) are the dominant technology for handset power amplier design by vir- tue of features like high power density, cut-off frequency, and efciency [1]. Unfortunately, these devices are plagued by electrothermal effects due to mesa isolation and low thermal conductivity of GaAs (one third of that of silicon), whichcombined with high operating currentscan lead to performance degradation, long-term reliability issues, and also sudden device failure (as an example, multinger transistors biased with a constant base current may suffer from current focusing, which can be performance-limiting due to the gain collapse or even destructive [26]). Since the late eighties, the literature has been populated by pa- pers centered on the thermal behavior of single- and multi-nger GaAs HBTs with the aim of achieving a thermal-aware design (e.g., [2 27]). Several studies have been focused on the metallization due to the relevant role played by the upward heat ow [11] (the poor GaAs conductivity hinders the heat transfer to the backside); in particular, most of them have proposed and/or analyzed solutions based on ther- mal shunts [8,12,1620,23,25]. Other works dealing with multi-nger transistors have promoted emitter or base ballasting [15,19,27], and nonuniform nger spacing or length for an assigned die and emitter area [22,27]. Some papers have also investigated the benecial effect of a more thermally conductive and/or shorter path from the heat dissi- pation region and the sink, which can be obtained with ip-chip (FC) packaging [9,10,14,16,18] or alternative solutions based on thermal vias [13,25]. Little attention was instead paid to other technology fea- tures like the specics of the emitter stack (with the exception of [18]), which cannot be disregarded since in modern InGaP/GaAs HBTs the ternary InGaAs and InGaP emitter layers suffer from thermal con- ductivities even poorer than GaAs (and thus thermal shunt solutions are less effective); moreover, since designs are moving to FC, the ther- mal impact of the emitter is expected to be amplied since the heat propagates through it to the sink. In addition, no studies have been pub- lished that report an exhaustive thermal comparison between the con- ventional wire-bonding (WB) technologystill largely adopted due to its exibility, existing infrastructure, and low costand the FC assembly, which benets from a smaller package size and aims to boost the performance. In [28],a rst attempt was made to ll some of the above gaps by in- vestigating the inuence of emitter stack, metallization, and emitter lay- out upon the thermal behavior of simple unpackaged single-emitter InGaP/GaAs HBTs; an accurate and efcient analysis was conducted by Microelectronics Reliability 78 (2017) 233242 Corresponding author. E-mail address: vindales@unina.it (V. d'Alessandro). http://dx.doi.org/10.1016/j.microrel.2017.09.011 0026-2714/© 2017 Elsevier Ltd. All rights reserved. Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel