180 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 3, MAY 2006 Design and Optimization of Two-Bit Double-Gate Nonvolatile Memory Cell for Highly Reliable Operation Seongjae Cho, Il Han Park, Tae Hun Kim, Jae Sung Sim, Ki-Whan Song, Jong Duk Lee, Member, IEEE, Hyungcheol Shin, Member, IEEE, and Byung-Gook Park, Member, IEEE Abstract—In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND- and NOR-type memory cells. This paper is based on simulation works which can give a rea- sonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si N used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide–nitride–oxide dielectric flash memory cell at a good degree. Index Terms—Operating schemes, read disturbance, two-bit floating-gate-type nonvolative memory (NVM) cell. I. INTRODUCTION R ECENTLY,a novel multibit nonvolatile memory (NVM) based on a double-gate (DG) MOSFET is proposed to overcome the short-channel effects and to increase the memory density [1], [2]. When it comes to a DG MOSFET NVM cell in ultrasmall dimensions, read disturbance is one of the greatest concerns. However, the read disturbance originating from the interference between both floating gates for storage nodes has not yet been thoroughly studied. In this paper, we investigate the effects imposed on the read disturbance by various factors, such as the thickness of the silicon channel, channel doping concentration, and the difference of charge amount between a programmed state and an erased state in detail. Another cru- cial parameter in flash memory is the tunneling oxide thick- ness. However, we fixed the thickness to 7 nm, as can be seen in Table I, for good retention. Furthermore, according to the Inter- national Technology Roadmap for Semiconductor 2004 Update, the tunneling oxide thickness is predicted to be, for a NOR-type memory cell, 8–9 nm for 2006 and 8 nm for 2018 and, for the Manuscript received June 30, 2005; revised October 12, 2005. This work was supported by Samsung Electronics Corporation through the cooperative project “Research on Structure and Characterization of the Nonvolatile Memory De- vices.” The review of this paper was arranged by Guest Editor M. Tabe. The authors are with the School of Electrical Engineering and Com- puter Science, Seoul National University, Seoul 151-742, Korea (e-mail: felixcho@smdl.snu.ac.kr). Digital Object Identifier 10.1109/TNANO.2006.869943 TABLE I KEY PROCESS PARAMETERS Fig. 1. Two-bit DG NVM cell structure. case of a NAND-type memory cell, 6–7 nm for 2006 and in- variable up to 2018 [3]. This reflects the fact that retention is a more critical requirement in flash memory cells, so that the tunneling oxide thickness cannot be easily controlled for scala- bility. Based on these criteria, we present an appropriate device structure and possible operating conditions for stable operation of the 2-b NVM cell. To this end, we used Silvaco Atlas, which is a two-dimensional (2-D) numerical analysis simulation tool [4]. II. STRUCTURE AND OPERATION SCHEMES Fig. 1 and Table I show the schematic view of the NVM cell proposed for this study and describe the critical dimensions of the structure, respectively. Although Table I appears before the following graphical analyses, the specification is based on the optimized results from the consecutive simulation works. We varied the channel thickness from 10 to 50 nm to determine the optimized conditions. For a nonnegative threshold voltage of NOR flash memory, higher channel doping is needed in the sub-100-nm regime. The bottom control gate (BCG) voltage for read operation and the channel thickness were found to be intimately related so as to control the read disturbance, as will 1536-125X/$20.00 © 2006 IEEE