Fast scheduler solutions to the problem of priorities for polarized data traffic Gérard Damm, John Blanton, Prasad Golla, Dominique Verchère, and Mei Yang Alcatel USA Research and Innovation Department 1201 E. Campbell Rd, Richardson, Texas 75081, USA {Gerard.Damm, John.Blanton, Prasad.Golla, Dominique.Verchere, Mei.Yang}@usa.alcatel.com Abstract Three fast scheduling algorithms are proposed to handle efficiently polarized traffic in an advanced architecture for multiple-server optical IP packet routers. These schedulers must be capable of transferring several fixed-sized packets per port per time slot rather than one cell per time slot. An optical burst packet (OBP) contains a number of cells, obtained either from a network protocol or from segmentation. To optimize the resource utilization, it is important to maximize the filling ratio of these OBPs, but also important to adjust the right time-out to trigger the transfer of non-full packets. Moreover, the hardware implementation must be feasible and cost-effective. The solutions presented in this paper are detailed and compared by means of simulations. The first of them, MultiSLIP, is a generalization of iSLIP to the multiple-server architecture. The second one, PDRR, is a generalization of DRR (Dual Round Robin) to multiple-server architecture with priorities. The third one, FR-DRR (Flexible Ring DRR), features a new arbitration scheme based on a circular list of pending requests. I. Introduction The switch fabric model considered in this paper is a set of N input ports are connected to a switching device such as an optical matrix (OM), which is connected to N output ports. The input memory is organized in VOQs (Virtual Output Queues) so as to avoid HOL (Head Of Line) blocking [1]. In the classical architecture, each port has one server, which allows the transfer of one cell per port per matrix cycle (or time slot). The scheduling problem comprises picking a requesting VOQ in each input port at each time slot while optimizing a set of different properties such as throughput maximization, fairness, non-starvation, and hardware feasibility [2]. Figure 1. Multiple-server architecture New advances in hardware systems have made it possible to have more than one server per port, so as to match the high capacity of the OM. This change imposes the design of innovative scheduling algorithms. In the multiple-server architecture, the scheduler can pick several OBPs (Optical Burst Packets) from different VOQs in each input port, and can also transfer several OBPs from one VOQ, with all the possible combinations. Any input server can take an OBP from any VOQ in its port and send it to any output server through the OM. Figure 1 represents the architecture with N ports and H servers per port. The OBP is the data unit transferred by a server each time slot. It contains ECPs (Elementary Composite Packets), which in turn contain a number K of cells. This composition mechanism is usually referred to as burstification [3,4]. Figure 2 shows the structure of an OBP. For the purpose of architecture comparison, the capacity of a port (in bit/s) is supposed to be independent from H. Therefore, an OBP contains N/H ECPs (H is supposed to be a factor of N) so that each port can always send at most N ECPs at each time slot, whatever H. Intuitively, the finest granularity and highest flexibility should be obtained when H=N, i.e. when an OBP contains only one ECP. This result is confirmed by the simulations. In this paper, we will consider architectures in which N=16 and H∈{2,4,8,16}. Figure 2. Optical Burst Packet structure The specification of a core router includes a time-out limit L, which guarantees that, with a given probability, the transit time of all incoming data is smaller than or equal to L seconds. When there is uneven (polarized) data traffic into the different input queues, it will eventually become necessary to trigger the transfer of non-full OBPs through the matrix in order to clear data cells before they grow stale. This reduces the throughput of the switch, since non-full OBPs represent unused capacity. Due to space limitation, we keep out of the scope of this paper all the functionalities related to the ingress and egress stages, including reassembly of IP packets previously segmented into cells. To meet the conflicting requirements of maximizing the throughput of the switch matrix and respecting the time limit, we propose three scheduling algorithms, described in section II. We compare them by simulation in Section III. Measured by the average data cell transit time, the performance of each scheme is assessed for a number of server and time slot configurations under different degrees of traffic load and polarization. Section IV presents a list of hardware implementation issues and section V concludes the study. II. Description of the Schedulers 2.1. Computation of Grants MultiSLIP The first idea to deal with multiple-server architecture is to generalize the single server iSLIP algorithm [5]. This solution, input port 1 1 2 N 1 2 H ... ... ... input port N 1 2 N 1 2 H ... ... OM output port 1 1 2 H ... ... output port N 1 2 H ... OBP 1 K 2 1 K 2 ECP #1 ECP #N/H ... ... ...