-)#2/0/7%2")4!$#/.6%24%2 μ7!4±6!.$+3!-0,%33 L. Grisoni, A. Heubi, P. Balsiger and F. Pellandini Institute of Microtechnology, University of Neuchatel, Breguet 2, CH-2000 Neuchatel, Switzerland Phone: +41 32 718 34 04, Fax: +41 32 718 34 02, E_Mail: peter.balsiger@imt.unine.ch !BSTRACT: Micro power converters are required for power sensitive, battery-operated devices. Keeping this goal in mind IMT first developed a RSD cyclic converter featuring 13 bits of dynamic range and 60 dB of SNR. The relative precision behavior is due to technology limitations (capacitor mismatch, finite DC gain of OTA). However, digital correction is possible and this paper presents the implementation in a low voltage 1 μm CMOS technology of a new linear ADC. The targeted performances were 14 bits and 45 μW @ 16 kHz & ±1.25 V power supply for a die size of 1.17 mm 2 . “Layout level” simulations however showed that to reach the 14 bits, a power supply of ±1.5 V is required and results in a 65 μW power consumption. )NTRODUCTION Progress in low power micro-electronics technologies and digital signal processing has opened the way to numerous digital portable applications. Targeted low power A/D converters are thus required to improve the overall power consumption and consequently the battery life. In previous work, a Redundant Signed Digit (RSD) algorithmic converter was developed at IMT [Heub96]. It features 13 bits dynamic range, 60 dB SNR and its power consumption at ±1.25 V and 16 kHz is less then 50 μW. The limited SNR is well suited for audio application where masking effects take place. It is however a drawback for applications such as instrumentation. The ‘relative precision’ (error proportional to input signal) results from imprecise doubling operations and finite DC gain. Consequently each bit b i computed by the RSD converter has a (2+e) -i weight, while in an ideal case this weight would have been 2 -i . A simple base translation can thus be performed to obtain the correct word and achieve a linear characteristic over the whole input range. This paper focuses on the implementation of the above base translation in a low voltage 1 μm CMOS technology. Section 2 describes the relative precision RSD converter as developed by A. Heubi [Heub96] while the correction algorithm is explained in section 3. It’s implementation and the resulting chip are presented in section 4. Section 5 gives the test measurements while devices with a higher dynamic range or faster sampling frequency are considered in section 6. Finally, section 7 concludes the discussion. 2ELATIVEPRECISIONCONVERTER;(EUB= In conventional binary representation, a single word matches a numerical value. In [Gine88], a Redundant Signed Digit (RSD) code is proposed. Because of the redundancy, many words can represent a same value. For example, [0 1 0 0 0 1], [1 -1 0 0 0 1] or [0 1 0 0 1 -1] all represent the value 0.265625. i ≥ n i < n Vx >Vth Vx<-Vth V x = V in i = 0 b i = 1, Vx (i+1) =2Vx (i) -Vref i=i+1 b i = 0, Vx (i+1) =2 Vx (i) b i = -1, Vx (i+1) =2Vx (i) +Vref Figure 1.1 : Cyclic RSD conversion algorithm The advantage of the RSD conversion is that the very accurate comparison (inaccuracy smaller then a half LSB) that is normally performed in cyclic converter is replaced by two comparisons as shown in figure 1.1 [Gine92]. Hence, the design constraints on the comparators are drastically simplified and inaccuracies of up to half Vref are tolerated, regardless of the number of bits. Alexandre Heubi proposed a very efficient switched capacitor implementation of the above algorithm. The input signal is sampled at the beginning of the conversion cycle and thus no sample & hold is Published in 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), 39-42, 1997 which should be used for any reference to this work 1 brought to you by CORE View metadata, citation and similar papers at core.ac.uk provided by RERO DOC Digital Library