An Analytical State Dependent Leakage Power Model for FPGAs
Akhilesh Kumar and Mohab Anis
Department of Electrical and Computer Engineering
University of Waterloo, Waterloo, ON, Canada N2L3G1
{a5kumar, manis}@vlsi.uwaterloo.ca
Abstract
In this paper we present a state dependent analytical leakage
power model for FPGAs. The model accounts for subthreshold
leakage and gate leakage in FPGAs, since these are the two dom-
inant components of total leakage power. The power model takes
into account the dependency of gate and subthreshold leakage on
the probability of the state of circuit inputs. The leakage power
model has two main components, one which computes the prob-
ability of a state for a particular FPGA circuit element, and the
other which computes the leakage of the FPGA circuit element for
a given input using analytical equations. This FPGA power model
is particularly important for rapidly analyzing various FPGA ar-
chitectures across different technology nodes.
1 Introduction
The scaling of technology has led to an exponential increase
in leakage power, and managing leakage power has emerged as a
key design challenge. In earlier FPGA designs,leakage was not a
concern, however, contemporary FPGAs are being implemented in
sub 100nm CMOS technologies, and the leakage power cannot be
ignored. The work in [2] showed that a 90nm FPGA consumes
too much leakage power to be successfully used in mobile applica-
tions. Managing leakage power in FPGAs is therefore necessary for
FPGAs to retain its competitive advantages over high performance
custom VLSI designs and also for gaining popularity in domains
such as wireless personal communications and low power biomed-
ical applications. It is important, therefore, to accurately model the
various components of leakage power and to analyze its behavior in
FPGAs, so that leakage reduction techniques can be effective and
efficient.
The work in [7] discussed various leakage current mechanisms
and leakage reduction techniques for CMOS circuits. Analytical
equations for leakage computation have been studied and devel-
oped in detail, which can model the complex behavior of various
components of leakage current in a MOS transistor. These models
are based on physical and empirical parameters [8]. Typically, the
leakage power consumption of any circuit is not only dependent on
the physical parameters of the circuit, but is also heavily dependent
on the inputs to the circuit. The work in [9] shows that the leakage
current can vary by an order of magnitude depending on the input
to the circuit and demonstrated that certain inputs are the dominant
leakage states for a gate.
There have been very few works targeted at modeling leakage
Figure 1: FPGA architecture under consideration
power for the FPGAs. The work in [5] modeled the dynamic and
the leakage power. However, it considered only subthreshold leak-
age and did not consider the dependency of subthreshold leakage
on the state of the circuit, rather it calculated an average leakage
considering that all the transistors were leaking and the Vgs was
considered for as half of V
th
for leakage computation. This pro-
duces inaccurate estimation of leakage current. The work in [3]
and [2] calculated total power using look-up table based approach
using SPICE simulations to characterize the power of the FPGA
circuit elements. However, it did not develop any state dependent
leakage power model and the methodology described is technology
dependent.
Motivated by the above mentioned limitations of the previous
works, this work develops an analytical model for leakage power
calculation for FPGAs, that takes into account the dependency of
the leakage power on the state of the circuit. The contribution of
the paper can be summarized as: (1) Developing analytical models
and methodology to compute subthreshold and gate leakage power
for FPGAs, independent of the technology node,(2) computation of
state dependent subthreshold and gate leakage, and (3) analysis of
sources of leakage in FPGAs.
2 Targeted FPGA Architecture
The FPGA architecture is very regular in structure. Fig. 1 shows
the targeted FPGA architecture for this work. It has two main com-
ponents - logic blocks (CLBs) and routing resources. The logic
blocks implement the functionality of the given circuit while the
routing resources provide the connectivity for implementing the
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