International Journal of Recent Advances in Engineering & Technology (IJRAET) _______________________________________________________________________________________________ _______________________________________________________________________________________________ ISSN (Online): 2347 - 2812, Volume-2, Issue - 4, 2014 35 Implementation of CRC and Viterbi algorithm on FPGA S. V. Viraktamath 1 , Akshata Kotihal 2 , Girish V. Attimarad 3 1 Faculty, 2 Student, Dept of ECE, SDMCET, Dharwad, 3 HOD Department of E&CE, Dayanand Sagar College of Engineering, Bangalore, Karnataka, India Email: svvmath@gmail.com Abstract— Cyclic Redundancy Codes (CRC) code provides a simple, yet powerful, method for the detection of errors during digital data transmission and storage. Convolutional Coding and Decoding (CODEC) is a Forward Error Correction (FEC) technique that is particularly suited for a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). The Viterbi Algorithm (VA) has been widely applied for decoding convolutionally encoded data in digital communication systems over the last 30 years. In this paper the implementation of CRC and Viterbi decoder on FPGA is presented. CRC-32 and Viterbi hard decision decoding algorithm for rate 1/2 implemented on FPGA. Also for higher SNR at the decoder side the concept of serially concatenated CRC- Convolutional Coding (CC) with lookup table is also proposed. Keywords— CRC, FPGA, Viterbi, Trellis, Constraint length. I. INTRODUCTION The evolving world of telecommunications requires increasing reliability and speed in communications. Reliability in information storage and transmission is provided by coding techniques. Information is usually coded in a bit streams and transmitted over the communication medium, channel. The communication media is prone to errors due to noise present in the analog portion of the channel. Therefore errors have to be detected and corrected while decoding. CRC has the advantages of easy coding and decoding as well as strong abilities of checking errors and correcting errors. Therefore, it was widely used in the field of communications. Reliability in information storage and transmission is provided by coding techniques. CRC is an error-detecting code designed to detect accidental changes to raw computer data, and is commonly used in digital networks and storage devices such as hard disk drives. Blocks of data entering these systems get a short check value attached, derived from the remainder of a polynomial division of their contents; on retrieval the calculation is repeated, and corrective action can be taken against presumed data corruption if the check values do not match. The CRC was invented by W. Wesley Peterson in 1961. CRC is an error detecting code that is widely used to detect corruption in blocks of data that have been transmitted or stored. The Error Control Coding techniques (ECC) rely on the systematic addition of redundant bits at the transmitting side. The task of channel coding is to encode information sent over a communication channel in such a way that in the presence of channel noise, errors can be detected and possibly corrected. There are two coding methods - backward error correction codes and forward error correction codes. Backward error correction codes requires only error detection, if an error is found then the transmitter is requested to retransmit the message. Forward error correction codes require the decoder to be capable of correcting errors. There are several error correcting codes and these are classified under two basic categories namely block codes and convolutional codes. Convolutional codes [1] differ from block codes [2] in the sense that bit streams are not partitioned into binary words instead redundancy is added continuously to the whole stream. Convolutional codes are widely used error control coding technique in channel coding because of low complexity and error controlling capability. Viterbi decoding algorithm [3, 4] is the simplest and best algorithm for decoding of convolutional codes. The Viterbi algorithm first appeared in the coding literature in a paper written by Andrew J. Viterbi in 1967 [5]. Since then, due to its easiness in implementation, it has been applied to many different areas related to decoding problems. The 8-bit parallel CRC-32 is proposed in [6] to meet the high throughput of USB3.0. Exhaustive survey of all CRC polynomials from 3 bits to 15 bits is presented in [7]. A set of 35 new polynomials in addition to 13 previously published polynomials are also described. The method that realizes the ability of multiple bits error correction using cyclic redundancy check codes is presented in [8]. The structures of 8-bit CRC are presented in [9]. The joint decoding scheme of serially concatenated CRC and convolutional code (CC) has been investigated in [10 11]. This paper is organized as follows. Section II gives the proposed work. Section III gives the CRC coding. The