Effects of isothermal aging and temperature–humidity treatment of substrate on joint reliability of Sn–3.0Ag–0.5Cu/OSP-finished Cu CSP solder joint Jeong-Won Yoon a , Bo-In Noh a , Young-Ho Lee b , Hyo-Soo Lee c , Seung-Boo Jung a, * a School of Advanced Materials Science and Engineering, Sungkyunkwan University, 300 Cheoncheon-dong, Jangan-gu, Suwon, Gyeonggi-do 440-746, Republic of Korea b ACI R&D Center-Development Team, Samsung Electro-Mechanics Co., Nocksan Industrial Complex 1623-2 Songjeong-dong, Kangseo-gu, Busan 618-721, Republic of Korea c Nano Material Team, Advanced Material Center, Korea Institute of Industrial Technology, 7-47 Songdo-dong, Yeonsu-gu, Incheon 406-840, Republic of Korea article info Article history: Received 11 January 2008 Received in revised form 15 July 2008 Available online 9 September 2008 abstract This study examined the effects of isothermal aging and temperature–humidity (TH) treatment of sub- strate on the joint reliability of a Sn–3.0Ag–0.5Cu (wt.%)/organic solderability preservative (OSP)-finished Cu solder joint. Two types of OSP-finished chip-scale-package (CSP) substrates were used, those subjected and not subjected to the TH test. This study revealed an association between the interfacial reaction behaviors, void formation and mechanical reliability of the solder joint. Many voids were formed at the interface of the OSP-finished Cu joint subjected to the TH test. These voids were caused by the oxi- dation of the OSP-finished Cu substrate during the TH test. In the shear tests, the shear force of the joint with the substrate not subjected to the TH test was slightly higher than that with the TH test. The mechanical reliability of the solder joint was degraded by voids at the interface. Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction With the continued miniaturization of electronic components and their increasing functionality, the electronics industry is rap- idly switching towards fine pitch devices [1]. Area array compo- nents have become a viable solution to the requirements of industry. With area array devices, the solder joint reliability is one of the most critical factors. This is because with finer pitches, a smaller amount of solder is deposited with a correspondingly smaller solder ball size [2]. The deleterious effects of lead (Pb) on the environment and human health have accelerated research and development on Pb- free packaging technology. The research effort has been successful in identifying several candidates (such as Sn–Bi, Sn–In, Sn–Zn, Sn– Ag, Sn–Ag–Cu and Sn–Cu) as a replacement for conventional Sn–Pb solders in ball-grid-array (BGA) and flip-chip technology [3–11]. Among them, the Sn–Ag–Cu ternary alloy is the most general Pb- free solder, which has the advantages of good wetting property, superior interfacial properties, high creep resistance and low coars- ening rate [3]. Among the important issues for the development of Pb-free packaging systems, the development of an appropriate Pb- free surface finish on a printed circuit board (PCB) is important. In soldering electronics devices on PCBs, the manufactures use many types of surface finishes (e.g. plating). These finishes can strongly influence the interfacial reaction and wetting properties. The thick- ness of the intermetallic compound (IMC), composition, micro- structure, mechanical properties and reliability of solder joints are strongly dependent on the surface finish layers [12–16]. Although an Au/Ni layer is currently a popular choice, it has been found that this system causes embrittlement through the forma- tion of a (Au,Ni)Sn 4 IMC at the interface during solid-state aging, which can be fatal for solder joints [17,18]. An organic solderability preservative (OSP) coating is another promising option for Pb-free surface finishes. Choosing the OSP eliminates the possibility of Au– Sn IMCs embrittlement and also has the advantages of excellent solderability, low cost, simple processing and environment friendly [19,20]. The joint reliability is one of the most critical criteria in the development of a package materials system [6,10]. Since the join- ting process is a direct consequence of an interfacial reaction be- tween the solder and substrate, understanding the interactions between these materials is integral to the development of a reliable jointing system. The solder joint reliability is a result of many fac- tors including various design and process parameters. In particular, voids, which arise as a result of the process parameters, have been observed to be a critical factor that affects the solder joint reliability [2,13,21–25]. Voids can degrade the mechanical robustness of the board level interconnections and affect the reliability and conduct- ing performance of the solder joint [2]. However, it has been diffi- cult to examine the effect of voids on the reliability of solder joints because it has been an uncontrolled factor during the assem- bly process and it has been difficult to isolate the effect of voids on 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.065 * Corresponding author. Tel.: +82 31 290 7359; fax: +82 31 290 7371. E-mail address: sbjung@skku.ac.kr (S.-B. Jung). Microelectronics Reliability 48 (2008) 1864–1874 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel