2020 IEEE International Conference on Semiconductor Electronics (ICSE) 978-1-7281-5968-3/20/$31.00 ©2020 IEEE Temperature Impact on The I ON /I OFF Ratio of Gate All Around Nanowire TFET Firas Natheer Abdul-kadir Agha Department of Electrical Engineering, College of Engineering University of Mosu Mosul, Iraq firas_nadheer@uomosul.edu.iq Yasir Hashim Department of Computer Engineering, Faculty of Engineering, Tishk International University Erbil-Kurdistan, Iraq yasir.hashim@ieee.org Mohammed Nazmus Shakib Faculty of Electrical & Electronics Engineering Technology, Universiti Malaysia Pahan 26600 Pekan, Pahang Darul Makmur, Malaysia nazmus@ump.edu.my Abstract—This research paper presents the effect of working temperature on the ION, IOFF and ION/IOFF ratio of gate all around nanowire TFET. The (Silvaco) simulation tool has been used to investigate the temperature characteristics of a transistor. The working temperature range of this study is from -50 to 150 step-up 25 o C. The final results indicate that the negative effects of increasing working temperature of gate all around nanowire TFET due to decreasing of the ION/IOFF ratio. Hence, the results for ION/IOFF ratio vs. working temperature characteristics may lead to the use of TFET in electronic circuits with lowest possible working temperature to obtain higher ION/IOFF ratio. Keywords— Nanowire, Transistor, Temperature, TFET, IOFF , ION. I. INTRODUCTION Nowadays, in nanoelectronic technology, a new structures of transistors in nano-scale dimensions has been investigated to overcome the normal MOSFET structure weaknesses in nano-scale [1-3]. One of these structures is the nanowire Tunnel Field Effect Transistors (TFET). TFET are good alternatives to substitute the normal structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and it has a potential candidate for electronic devices, because the TFET have low OFF current (IOFF), small sub-threshold swing SS (less than 60 mV/decade), low power consumption and reduced Short Channel Effects (SCE) [4-8]. However, the main drawback of TFET is low ON current (ION). Hence, a Gate All Around (GAA) structure is exploited to improve the ION and it can be considered the ultimate solution for the improvement of ION/IOFF current ratio due to its excellent electrostatic coupling [9-10]. Another advantage of GAA transistor which make it be considered as a promising candidate is the advancements of the applications of complementary metal oxide semiconductor (CMOS) due to its ability to achieve better coupling between channel and gate. In comparison with a MOSFET, nanowire TFET device controls on the electrostatic of channel better than MOSFET device [11-12]. In MOSFET device the transport mechanism used for carrier diffusion is thermionic injection whereas the tunneling mechanism is used as a reliable technique of the carrier injection in TFET device [13-14]. However, the structure of TFET and MOSFET is similar, but the type of doping in Source and Drain is opposite and the switching mechanism is faster in TFET compared with MOSFET [15]. Moreover, in MOSFET device, the ON current (ION) increases when the temperature decreases, while in TFET device, the ON current (ION) increases when the temperature increases, due to the induced temperature which make on the reduction of the band gap [16]. Hence, this research pay attention to analysis and investigation of the effect of working temperature on ION, IOFF and ION/IOFF ratio of nanowire TFET with gate all around structure. Finally, the GAA structure of TFET will increase the density on-chip device with high controllability of gate [12]. So, the GAA TFETs are considered as the one of contenders for the throne of MOSFETs [17-18], II. METHODOLOGY A gate all around TFET device, has been designed and simulated by using Silvaco simulation tool by the specified dimension of nanometers scales as shown in Table I. Figure 3 shows a cross-sectional area of the geometric structure and limited dimension of the device, where the radius of the silicon intrinsic channel is (R), the gate length (Lg) and thickness of the gate oxide dielectric material SiO2 is (Tox). TABLE I. SIMULATION PARAMETERS OF TFET Parameter Value Channel radius (R) (35) nm Oxide thickness (TOX) (4.5) nm Channel Doping (P) 10 17 cm −3 Drain Doping (P + ) 10 19 cm −3 Source Doping (N + ) 10 19 cm −3 Drain length 80 nm Source length 80nm Channel length (L) (200) nm Doping concentration of the channel is 10 17 cm -3 and doping concentrations for drain and source is 10 19 cm -3 , respectively. The dimensions of the channel Lg is 200 nm, radius of the channel R is 35nm, SiO2 thickness Tox is 4.5 nm and dimensions for drain and source lengths (LS and LD) is 80 nm, respectively. In this work, we used various temperature degrees, from - 50°C to 150°C step-up by 25°C. The voltage taken at the drain terminal (VDS) is 1 V and voltage applied at the gate terminal (VGS) is varied from 0 V to 1 V in step-up 0.1 V. 61