ORIGINAL PAPER Linearity Parameters Evaluation due to Lateral Straggle in Ge-Source DMDG-TFET Rajesh Saha 1 Received: 5 October 2020 /Accepted: 20 November 2020 # Springer Nature B.V. 2020 Abstract TFET is very favourable device than MOSFET in terms of low power design and applications. The accurate fabrication of device results in satisfactory electrical characteristics. The diffusion of source/drain regions through the ion implantation technique, extent to the channel section, which eventually changes the behaviour of device. In this letter, the linearity behaviour of Ge- source dual material double gate (DMDG) TFET is highlighted for the variation in lateral straggle parameter (σ) from 0 to 5 nm. The linearity parameters such as higher order harmonics (g m2 and g m3 ), voltage intercept point (VIP 2 and VIP 3 ), input intercept power (IIP 3 ), intermodulation distortion (IMD 3 ), and 1-dB compression point are studied in Ge-source DMDG-TFET taking σ as parameter. Keywords Ge-source . Lateral straggle . Linearity parameters . TFET 1 Introduction The scaling of MOSFET is hampered by short channel effects (SCEs) and thermionic emission of charge carrier limits sub- threshold swing (SS) equal to to 60 mV/dec. at 300 °K [1]. In this aspect, a new concepts and alternative device structure, TFET is proposed. The principle of operation of TFET is band-to-band-to (BTBT) and immune towards SCEs with ther- mal SS less than 60 mV/dec. [2]. However, TFET is suffered from low value of ON current and high ambipolar current. To have enhanced performance of TFET, Ge source [3] TFET, dual material gate (DMG) TFET [4], Silicon on Insulator (SOI) TFET [5], circular gate TFET [6], cylindrical TFET [7], gate modulated (GM) TFET [8], SiGe channel TFET [9], double gate (DG) TFET [10] are reported in literature. The presence of two gates in DG-TFET enhanced the tunneling probability, which leads to increased drain current in TFET [10]. The presence of low work function gate material near the source region in DMG-TFET, improves the short channel characteristic and ambipolar behaviour in TFET [ 4 ]. Considering these structural importance, a new device named as Ge-source dual material double gate (DMDG) TFET is pro- posed in literature. TFET is also one of the promising candidate in terms of RF and analog applications compared to MOSFET. For low voltage applications, TFET based circuit like amplifier, current mirror and track-hold are highlighted in literature [11]. Likewise, nanowire TFET channel material beyond Silicon material is more favorable for RF and analog applications than conventional TFET due to having large gain and more cut off frequency [12]. The III-V heterojunction TFET has improved analog as well as digital performance compared to Silicon FinFET for low value of supply voltage 0.4 V [13]. The device characteristic depends on fabrication process technology. It is very problematic to control the certain tilt angle of ion implantation process during fabrication [14]. In order to avoid the channeling effect, the non-zero tilt angle must be minimize so that device performance can be main- tained. This non-zero angle introduced source/drain extension into the channel, which improves the ON current at the cost of degradation in SCEs because of reduction in channel length [15]. Besides, these extension give rise to overlap parasitic capacitances, which affects the switching speed of the device [15]. The high frequency and analog performance of DG MOSFET with symmetric and asymmetric configuration are improved, whereas, the speed is deteriorates as σ is increased [16]. Similarly, for DG TFET the increase in σ improves the analog/RF performance [ 17 ], whereas, the linearity * Rajesh Saha rajeshsaha93@gmail.com 1 Electronics and Communication Engineering Department, Malaviya National Institute of Technology Jaipur, Jaipur, Rajasthan 302017, India Silicon https://doi.org/10.1007/s12633-020-00859-7