Hindawi Publishing Corporation VLSI Design Volume 2010, Article ID 460312, 9 pages doi:10.1155/2010/460312 Research Article Error Immune Logic for Low-Power Probabilistic Computing Bo Marr, Jason George, Brian Degnan, David V. Anderson, and Paul Hasler School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA Correspondence should be addressed to Bo Marr, marr.bo@gmail.com Received 27 May 2009; Accepted 19 November 2009 Academic Editor: Gregory D. Peterson Copyright © 2010 Bo Marr et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case. 1. Introduction As digital technology marches on, ultra-low voltage opera- tion, atomic device sizes, device mismatch, and thermal noise are becoming commonplace and so are the significant error rates that accompany them. These phenomena are causing ever increasing bit-error rates, and with billion-transistor digital chips being produced today, even a 1-in-100-million bit error rate becomes costly. This paper will present a novel discovery of boolean logic that certain logic gates are more robust to error than others, and in fact it will be shown that some logic even improves the error rate just through natural computation. The paper will show how these principles translate into CMOS and other implementations, but these principles are independent of technological implementation since they are properties of boolean logic itself. Thus these design principles will stand the test of time. The motivation behind studying computing architec- tures robust to error then becomes clear, especially as tech- nological breakthroughs have recently shown that extreme power savings can be traded for a certain level of error— known as probabilistic computing [1]. Paying more attention to error rates is critical if scaling power consumption and devices is to continue [2]. Recently, ultra-low power computing has been achieved by lowering the supply voltage of digital circuits into near threshold or even the subthreshold region [1, 3]. Indeed a fundamental limit to voltage scaling technology has been proposed: the thermodynamic limit of these devices [4]. When the supply voltage becomes comparable to thermal noise levels in these types of ultra-low power designs, devices start to behave probabilistically giving an incorrect output with some nonzero probability [4, 5]. Kish predicts that the thermal noise phenomenon will result in the “death” of Moore’s law [6]. The International Technology Roadmap for Semiconductors predicts that thermal noise will cause devices to fail catastrophically during normal operation— without supply voltage scaling—in the next 5 years [6, 7]. A paradigm-shifting technology has been introduced in part by the authors called probabilistic CMOS or pcmos to combat the failure in voltage scaling due to the kT/q thermal noise limit. Experiments have already been completed that show that this thermal noise barrier can be overcome by computing with deeply scaled probabilistic CMOS devices. It was shown, in part by the authors, that probabilistic operation of devices allows for applications in arithmetic and digital signal processing that use a fraction of the power of their deterministic counterparts [1, 8]. This paper builds upon this work, and offers improved solutions for ultra-low power datapath units.