New techniques for selecting test frequencies for linear analog circuits Mohand Bentobache * , Ahc` ene Bounceur † , Reinhardt Euler † , Yann Kieffer ‡ and Salvador Mir § * LAMOS Laboratory, University of Bejaia, 06000, Algeria, Email: mbentobache@yahoo.com † Lab-STICC Laboratory, University of Brest, 20, Avenue Victor Le Gorgeu, 29238, Brest, France, Email: Ahcene.Bounceur,Reinhardt.Euler@univ-brest.fr ‡ LCIS Laboratory, University of Grenoble Alpes, 26900 Valence, France, Email: Yann.Kieffer@esisar.grenoble-inp.fr § TIMA Laboratory, 46, av. F´ elix Viallet, 38031 Grenoble, France, Email: Salvador.Mir@imag.fr Abstract—In this paper we show that the problem of mini- mizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity. Index Terms—Set covering problem, Consecutive-ones prop- erty, Analog circuit testing, Linear programming, Interval graphs. I. I NTRODUCTION The optimization of test sets for integrated circuits is critical for reducing the large costs of production testing. For digital circuits, fault-based test pattern generation techniques are used. This structural approach is less common for analog circuits that are still tested using specification-based approaches. The variety of analog and mixed-signal blocks and the lack of general fault models have prevented a widespread use of structural techniques. However, there is a pressing need to adopt fault-based approaches also for analog circuits, providing measures of fault coverage for optimized test sets, especially in the context of SoC devices that embed digital and mixed-signal blocks in a single chip. Multi-frequency tests (i.e. multi-tone sinusoidal signals) have been classically considered for the test and diagnosis of linear analog devices such as analog filters. Since the effect of parametric and catastrophic faults varies as a function of frequency, it is possible to derive a minimal set of test frequencies either for the detection or for the diagnosis of all potential faults. To optimize the set of test frequencies, the ap- proaches based on sensitivity analysis have typically addressed parametric faults [1], [2]. However, these approaches are not accurate for very large deviations, such as those that result from catastrophic faults. On the other hand, the approaches based on fault simulation can handle catastrophic faults, but at the expense of very time consuming simulations when realistic faults at transistor-level are considered. Today, it is evident that fault simulation of analog circuits is becoming essential in order to optimize test sets relying on new techniques to accelerate fault simulation. In this context, this paper proposes a new technique for the optimization of multi-frequency tests for linear analog circuits. Fault simulation is used to obtain the frequency intervals for the detection of each fault. New efficient algorithms are then presented for the selection of the optimal set of test frequencies within these intervals for the detection of all faults. A simple case-study is used to illustrate the algorithms. Numerical sim- ulations with randomly generated problem instances demon- strate the good time complexity of the proposed algorithms, with a large improvement over previous approaches [3]. We notice that the test optimization algorithms are general, ap- plicable to any case-study requiring an optimization of multi- frequency tests based on fault simulation data. This technique is today feasible for analog filters, but it is also applicable to other analog devices such as analog-to-digital converters or radio-frequency front-ends requiring multi-tone tests, provided that fault simulation data are made available. The paper is organized as follows: in Section 2, the math- ematical formulation of the Set Covering Problem (SCP) is reviewed and some definitions are given. In Section 3, we present the mathematical formulation of the problem of minimizing the number of frequency intervals necessary to detect the faults of an analog circuit, and we study the specific structure of the related coefficient matrix. In Section 4, we present two approaches for solving the problem: the Linear Programming (LP) approach and the interval graph approach. In Section 5, we present a case-study of testing a biquadratic filter. In Section 6, we carry out a large-scale numerical study in order to compare both approaches and to evaluate their time complexity. Finally, Section 7 concludes the paper and provides some perspectives. hal-00855154, version 1 - 29 Aug 2013 Author manuscript, published in "International Conference on Very Large Scale Integration (VLSI-SoC), Turkey (2013)"