JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 33, NO. 5, MARCH1, 2015 991 Optical and Electronic Packaging Processes for Silicon Photonic Systems Nicola Pavarelli, Jun Su Lee, Marc Rensing, Carmelo Scarcella, Shiyu Zhou, Peter Ossieur, Member, IEEE, and Peter A. O’Brien (Invited Paper) > Abstract—Fiber optic interconnection processes and hybrid inte- gration of electronic devices for high speed Si photonic systems are presented. Thermal effects arising from these hybrid integration processes are also investigated. An overview of ePIXfab which of- fers affordable access to an advanced Si photonic foundry service is also presented. This includes the presentation of fundamental photonic packaging design rules which can greatly reduce the time and cost associated with the development of complex Si photonic devices. Index Terms—Electronics packaging, photonic integrated cir- cuits, semiconductor device packaging, silicon photonics. I. INTRODUCTION S ILICON photonics enables the production of highly inte- grated photonic sub-systems leveraging-off many of the ad- vances made in CMOS electronics. This offers the potential for cost reduction through mass manufacture using well-established wafer processing techniques. However, packaging these devices can add significant cost to the overall module, as fiber coupling and electronic interconnect processes still present major tech- nological challenges. An additional challenge associated with dense packaging and integration includes management of ther- mal effects which can affect device performance and impact on reliability. Therefore, device designers must take account of packaging early in the design cycle as this can impact on the ability to successfully package devices in a timely and cost- effective manner. II. ACTIVE PLANAR FIBER COUPLING A key advantage of Si photonics is the large refractive index contrast between the Si waveguide core and cladding materials (e.g., air or silica). This facilitates the production of compact and highly integrated photonic systems. Furthermore, Si photonics leverages many of the manufacturing advances made in CMOS electronics [1]. However, this high index contrast presents a real Manuscript received October 6, 2014; revised November 12, 2014; accepted November 23, 2014. Date of publication February 15, 2015; date of current ver- sion March 4, 2015. This work was supported by the Science Foundation Ireland under Grants 12/RC/2276 and 11/SIRG/I2112 and the European Commission through the ESSenTIAL, Fabulous, PLAT4M FP7 Projects. The authors are with the Tyndall National Institute, University College Cork, Cork, Ireland (e-mail: nicola.pavarelli@tyndall.ie; junsu.lee@tyndall.ie; marc.rensing@tyndall.ie; carmelo.scarcella@tyndall.ie; shiyu.zhou@tyndall. ie; peter.ossieur@tyndall.ie; peter.obrien@tyndall.ie) Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JLT.2015.2390675 Fig. 1. Fiber array packaging to Si grating couplers using the angle polished fiber design resulting in a compact planar assembly. challenge when packaging single-mode fibers due to a large dimensional mismatch between the fiber and Si waveguide. One way of alleviating this problem is by using grating cou- plers [2]. Grating couplers provide a viable means of achieving an interface between single-mode fiber cores (typical diameter of 8 μm) and Si waveguides (typical cross-section dimensions of 0.22 μm × 0.45 μm). From a packaging perspective, grat- ing couplers have an additional advantage of relatively relaxed alignment tolerance, with an approximate penalty of 1 dB over a planar misalignment of ±2.5 μm. Efficient grating coupler de- signs require the optical fiber to be positioned 10° off-vertical, resulting in a non-planar packaging assembly. However, we have developed a planar fiber packaging process that uses 40° pol- ished fiber facets, as shown in Fig. 1, that induce total internal reflection, achieving the required 10° off-vertical coupling [3]. This planar fiber packaging process has been implemented for a wide range of Si photonic assemblies; a recent example is demonstration of a planar packaging solution for a hybrid III- V/Si semiconductor optical amplifier (SOA). Fig. 2 shows the hybrid device assembled in a modified butterfly package. The SOA Si waveguides are coupled to the input and output fibers using the planar packaging process and fixed in position using UV epoxy bonding. The fiber-to-fiber gain is approximately 10 dB for an injection current of 90 mA, which is close to the theoretical maximum for this grating coupler design [4]. To achieve the level of precision necessary for single-mode fibers, packaging usually requires an active alignment process, where an optical source (laser) and detectors need to be turned on and the optical fiber is moved in the three directions of space and three angles of rotation with respect to the grating coupler in order to obtain the maximum coupled power. As a consequence, 0733-8724 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.