HIGH SPEED ADCS DEDICATED FOR WIDEBAND WIRELESS RECEIVERS M. Sawan, A. Djemouai, K. El-Sankary, H. Dang, A. Naderi, Y.Savaria, and F.Gagnon Polystim Neurotechnology Laboratory, Department of Electrical Engineering, Ecole Polytechnique of Montreal, Montreal (QC), Canada ABSTRACT In this paper we present and discuss the design of different architectures of high-speed analog-to-digital converters (ADCs) dedicated for wideband wireless receivers such as software-defined radio systems. Our interest concerns three different architectures: a pipelined 10-bit, 50 MS/s, a Flash 6-bit, 1-GS/s, and a band-pass Sigma-Delta 6-bit, 2-GS/s. A first version of the pipelined ADC and the Flash ADC was fabricated. As part of the Sigma-Delta ADC, a resonator operating at 2-GHz was fabricated. In addition to the design of these ADCs, a PCB card that supports these ADCs within a wireless receiver prototype was designed and tested. The ADCs technology of fabrication is the CMOS 0.18um for the pipelined and the flash, and the CMOS 0.13um for the band-pass Sigma-Delta. I. INTRODUCTION The accessibility of high performance sub-micron integrated circuits (IC) and the high rate of the proliferation of mobile communication applications have created enormous needs for the development of new generations of wireless receivers. Examples of such receivers are the wireless personal area networks -WPAN- (2.4 GHz) and wireless local-area network -WLNA- (5 GHz). Presently, all around the world, large efforts are oriented for the development of efficient reconfigurable, multi-band and multi-standard wireless receivers known as software-defined radio (SDR). Practically, the most feasible solutions for these receivers are either direct conversion or intermediate frequency (IF) transceivers. Here, advantages of digital hardware and software programming resources are highly exploited in order to perform digitally almost all the receiver functionality. By doing so, the constraints of the receiver’s analog parts are highly relaxed since in this case, the digitization of the received signal is performed just after the receiver antenna. This means that in SDR systems, the analog-to- digital converter (ADC) is placed as close as possible to the antenna and all the processing and the required demodulation operations are performed digitally. However, in such cases, the performances of the receiver are principally determined by those of the ADC. In fact, for SDR receivers, the ADC should comply with stringent characteristics such as high-speed operation, large input bandwidth, high resolution, and high spurious-free dynamic range (SFDR). In order to deal with these constraints, concepts of sub-sampling and over-sampling are usually exploited in SDR applications [1, 2]. Other constraints such as power consumption and area have to be also considered. Among the existing ADC architectures, the pipelined, the Flash, and the Sigma-Delta architectures are the most favorable for the design of ADC that meet the SDR specifications. In this paper, we present and discuss our team’s ongoing project that aims the design of three types of ADCs dedicated for wireless SDR receivers. The ADC architectures which are considered here are: Pipelined, Flash and band-pass Sigma-Delta converters. In section II, we present a 10-bit, 50 MHz pipelined architecture. In section III, we present a 6-bit, 1 GS/s ADC. In section IV, we present the proposed architecture for a 6 bit, 2 GS/s band-pass Sigma-delta ADC. Finally we discuss in section V the design of a PCB dedicated to include the designed pipelined ADC in wireless receiver prototype. II. PIPELINED ADC One of the suitable ADC architecture for the present and next wireless receiver generations is the pipelined ADC [3] owing to its wide input bandwidth and high-resolution capability. In this context, a 10-bit, 50 MHz, pipelined ADC has been implemented and fabricated. As shown in Fig. 1, this ADC includes nine cascaded stages. Each stage is composed of one multiplying digital to analog converter (MDAC) and one fully-differential 1.5 bits ADC. D i G ADC DAC SHA V i V i+1 S/H Stage i Stage P V in V 1 V i V i+1 V p D i D P V daci MDAC Fig. 1. Block diagram of a pipelined ADC. The MDAC is built around switched capacitor techniques and the 1.5 bits ADC uses dynamic comparators and preamplifiers. The ADC includes also an input fully- differential sample-and-hold (S/H) that enables sampling for high frequency signals without distortions. Moreover, digital calibration was used to minimize the effect of the offset voltage and the finite gain of the operational amplifier of each stage. 0-7803-8935-2/05/$20.00 ©2005 IEEE.