IEEETRANSACTIONSONELECTRONDEVICES,VOL.51,NO.2,FEBRUARY2004 279 Briefs___________________________________________________________________________________________ Vertical Tunnel Field-Effect Transistor Krishna Kumar Bhuwalka, Stefan Sedlmaier, Alexandra Katharina Ludsteck, Carolin Tolksdorf, Joerg Schulze, and Ignaz Eisele Abstract—The realization of a novel vertically grown tunnel field–effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two–dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current–voltage ( – ) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temper- ature independent drain current–gate voltage ( – ) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics. Index Terms—Band-to-band tunneling, gated p-i-n diode, vertical tunnel field-effect transistor on silicon, zener tunneling. I. INTRODUCTION As the continuous down scaling of the conventional metal–oxide– semiconductor field-effect transistor (MOSFET) is approaching its fundamental limits, the need for a replacement device is growing. To overcome drawbacks like short-channel effects (SCE), and source-drain off-currents of the conventional MOSFET, a vertical field-effect transistor based on band-to-band tunneling has already been proposed [1], [2]. Also, for a conventional n-channel MOSFET, the input characteristics show exponential current increase only in the subthreshold region, (gate voltage, , is less then the threshold voltage, ).Thedraincurrent, ,isthengivenby[3] Inthelinearregion, , , is Here, istheelectronmobilityinthechannel, isthecapacitance ofthegateinsulator, and arethedevicewidthandchannellength respectively and factor. is constant for constant drain voltage, , and is the gate voltage dependent surface potential. ThetunnelFETontheotherhand,showsexponentialcurrentbehavior even for . This is similar to the input characteristics of a bipolar-junctiontransistor(BJT).Thecollector–current, ,variesex- ponentially with the base–emitter voltage ; ManuscriptreceivedJune24,2003;revisedOctober10,2003.Thereviewof thisbriefwasarrangedbyEditorR.Shrivastava. The authors are with the Institute of Physics, University of the German Federal Armed Forces, Munich, D-85577 Neubiberg, Germany (e-mail: Krishna.K.Bhuwalka@UniBw-Muenchen.de). Digital Object Identifier 10.1109/TED.2003.821575 Fig.1. SchematicrepresentationofaverticaltunnelFET.Thechannellength nm. where isthesaturationcurrentatconstantcollector-emittervoltage . Further, it has also been suggested that the discreteness of dopant atoms will limit the scaling of the conventional MOSFET [4]. At the scalinglimits,thenumberofdopantatomscontrolling maybeless then100.Thus,thestatisticalspatialfluctuationsofdopantatomsinthe channel region may lead to device-to-device variation of . For the tunnelFET, iscontrolledbythetunnelingbarrierwidthandheight in the thin delta doped region at the source end, and is independent of doping in the intrinsic channel region. Thus, the effect due to the discretenessofatomsposesnolongeralimitationtothescaling. Low off-state leakage currents, high speed due to exponential cur- rent increase, and a nearly temperature independent current–voltage (I–V) characteristics make this device a strong candidate for the fu- ture technology. In this paper we present the realization of the tunnel FET which shows superior properties compared to the conventional MOSFET by means of both experimentation as well as two–dimena- tional(2-D)computersimulations.Thebasicdevicestructure,itsfabri- cationprocessandsimulationmodelsusedarediscussedandtheresults presented. II. DEVICE STRUCTURE AND OPERATION The experimental devices were fabricated using molecular beam epitaxy (MBE). The various layers were grown on a boron doped silicon substrate which also acts as the source electrode -cm [5].TheMBElayerstackconsistsofa3nmhighly doped1 cm boron delta-layer ,100nmlightlydoped (1 cm ), regionanda300nm1 cm , doped drain electrode, thus forming a p-i-n diode. It should be noted that the region arises from the unintentional doping during the MBE growth.Aftermesaetching,a16nmthicksiliconoxidewasthermally grown. The gate electrode consists of 300 nm poly-silicon. Fig. 1 shows the schematic representation of the vertical tunnel FET. Fig. 2 shows a cross-sectional transmission electron microscope (TEM) pic- tureofthedevicestructure.Thedevicewidthwas40 m.Asufficient positivegatevoltageinducesanelectronchannelintheintrinsicsilicon at the Si- interface and creates a sharp tunnel junction between channel and layer (n-channel device). Similarly, by applying 0018-9383/04$20.00 © 2004 IEEE