IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 5, MAY 2005 909 Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering Krishna K. Bhuwalka, Jörg Schulze, Member, IEEE, and Ignaz Eisele Abstract—In this paper, we look into the scaling issues of a ver- tical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tun- neling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA m for sub-100-nm channel lengths were observed. Further, with a p SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content . We show here that the tunnel FET performance is nearly independent of channel length scaling and with p SiGe layer, scaling is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output charac- teristics, the device looks good for sub-100-nm low-power analog devices. Index Terms—Gate workfunction engineering, leakage cur- rents, scaling, SiGe, subthreshold swing, surface-tunnel transistor, tunnel bandgap modulation, vertical tunnel field-effect transistor. I. INTRODUCTION T HREE-TERMINAL gated p-i-n diodes based on band-to-band tunneling have been demonstrated as possible candidates for future CMOS technologies [1]–[6]. Molecular beam epitaxy (MBE) grown vertical tunnel field-ef- fect transistors (FETs) have also been proposed [7]–[9]. Due to the low growth temperature epitaxy allows abrupt doping profiles and delta-doped layers, where doping concentrations can be varied by a few orders of magnitude within a distance of 3–4 nm. Experimentally, extremely high and abrupt doping profiles with 3-nm -doped layers have been achieved [10]. Recently, we demonstrated a similar device with a highly doped p Si layer at the p-source end, having several interesting properties in comparison to the conventional MOSFET [11], [12]. The device consists of a gated p-i-n diode as shown in Fig. 1. It works as a transistor when the p-i-n diode is reverse biased. When the gate is positively biased, it shows gate-con- trolled surface band-to-band tunneling from the valence band in the heavily doped p source region to the conduction band Manuscript received August 25, 2004; revised February 10, 2005. The review of this paper was arranged by Editor R. Shrivastava. The authors are with the Institute of Physics, University of the German Federal Armed Forces, Munich D-85577 Neubiberg, Germany (e-mail: Kr- ishna.K.Bhuwalka@UniBw-Muenchen.de). Digital Object Identifier 10.1109/TED.2005.846318 Fig. 1. Schematic representation of a vertical tunnel FET with p Si–SiGe layer at the p -source end. in the channel. The gate voltage induces an electron inversion channel in the intrinsic silicon at the Si–SiO interface and creates a sharp p n tunnel junction at the p-source end. This is the n-channel operating mode of the device. When the gate is negatively biased, it shows tunneling from the valence band in the accumulation channel to the conduction band in the heavily doped n drain region. The tunnel junction is formed at the drain end. Thus, p-channel operating mode. In both cases the current flow is due to electrons tunneling from the valence band to the conduction band. The gate controls the band-to-band tunneling width and hence the tunneling currents. With mid- bandgap gate material, intrinsic channel and symmetric n and p doping profiles in the source and drain regions, the silicon tunnel FET has symmetric current–voltage (I–V) character- istics with respect to n- and p-channel operation modes. The operational principle of this device has been discussed in detail by means of band-diagrams [12] and band-to-band tunneling generation rate [13]. When the p-i-n diode is forward biased, the device shows gate-controlled resonant interband tunneling even at room temperature. At low temperatures, clear resonant peaks were observed [14]. Apart from nearly temperature independent and exponen- tially increasing characteristics and perfect saturation in the characteristics, the device performance was free from short-channel effects such as drain-induced barrier lowering (DIBL) and rolloff up to very short-channel lengths as the tunneling probability is significant in silicon only for tunneling widths less then 10 nm. Since the p-i-n 0018-9383/$20.00 © 2005 IEEE