Monolithic 3D Integration: A Path From Concept To Reality Max M. Shulaker 1,2 , Tony F. Wu 1,2 , Mohamed M. Sabry 1,2 , Hai Wei 1,2 , H.-S. Philip Wong 1,2 , Subhasish Mitra 1,2,3 Stanford University Department of Electrical Engineering 1 , Stanford SystemX Alliance 2 , Department of Computer Science 3 Abstract Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today’s designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energy- efficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs. I. INTRODUCTION The traditional path for improving the energy efficiency of digital systems through silicon CMOS (Dennard [Frank01]) scaling is becoming increasingly difficult [Kuhn12]. Hence, alternative technologies beyond silicon CMOS are being explored. For example, ultra-thin (~1 nm) 1D semiconductors such as carbon nanotubes (CNTs) represent a significant departure from today’s silicon CMOS technology, promising improved device scalability and performance [Wong11]. Carbon nanotube field-effect transistors (CNFETs) are projected to improve the energy-delay product (EDP, a measure of energy efficiency) of very-large-scale integrated (VLSI) digital systems by an order of magnitude vs. silicon CMOS [Chang12]. CNFETs are also unique among emerging nanotechnologies since digital circuits and systems fabricated using CNFETs have been demonstrated [Shulaker13a-b, Shulaker14a]. Additionally, high-performance and highly- scaled CNFETs have also been demonstrated [Shulaker14b-c, Franklin12a]. Therefore, CNFETs are promising candidates for building the next-generation of high-performance and energy- efficient digital systems. Even with improved next-generation logic devices, system- level performance will remain severely constrained by the growing memory-logic communication bottleneck [Stanley- Marble11, Dally11]. To overcome this bottleneck, revolutionary digital system architectures with highly fine- grained integration of logic circuits and massive amounts of memory is required. 3D integration, whereby circuits are stacked vertically over one another, can achieve such increased level of integration [Banerjee01]. Today, 3D integration typically relies on vertical stacking of various circuit layers using vertical through silicon vias (TSVs) 1 . TSVs occupy a relatively large footprint: for example, typical TSVs are 5 m in diameter with a 20 m inter-TSV pitch [Xu13]. The large dimensions of the TSVs limit the density of vertical connections. To achieve fine-grained integration, denser connections between layers is necessary. Monolithic 3D integration, whereby each vertically-stacked layer of the 3D IC is fabricated directly over the previously fabricated layers, enables such future systems by allowing nano-scale inter-layer vias (ILVs) to be used to connect vertical circuit layers (i.e., no TSVs are required). These nano-scale ILVs have the same pitch and dimensions as tight-pitched metal layer vias, and are therefore orders of magnitude smaller than TSVs [Panth13, Batude11]. Given the ratio between TSV and ILV pitch, monolithic 3D integration enables massive vertical integration, achieving orders of magnitude (~1,000X) denser vertical connections compared to TSV-based 3D ICs. Fine-grained monolithic 3D integration of logic gates has been discussed in [Bobba11, Lee13]. However, such monolithic 3D integration (restricted to logic gates only) has limited benefits. In contrast, the massive connectivity enabled by monolithic 3D integration of logic and memory (and memory interface circuits) can directly translate into unprecedented memory bandwidth [Ebrahimi14], which in turn translates into significant improvements in performance and energy efficiency. While monolithic 3D integration is an attractive technological option, processing obstacles have posed major roadblocks: circuits on the upper-layers must be fabricated at a 1197 978-3-9815370-4-8/DATE15/ c 2015 EDAA