752 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 1.6 Gb/s/pin 4-PAM Signaling and Circuits for a Multidrop Bus Jared L. Zerbe, Member, IEEE, Pak S. Chau, Member, IEEE, Carl W. Werner, Member, IEEE, Timothy P. Thrush, H. J. Liaw, Member, IEEE, Bruno W. Garlepp, Member, IEEE, and Kevin S. Donnelly, Member, IEEE Abstract—A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motiva- tion for multi-PAM signaling is discussed. The system uses single-ended reference current-mode signaling with three dc references for maximum bandwidth per pin. A testchip with six I/O pins was fabricated in 0.35- m CMOS and tested in a 28- evaluation system using on-chip pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices. Index Terms—Integrating receivers, multilevel systems, parallel link, pulse amplititude modulation, receivers. I. INTRODUCTION T HERE has been a great deal of interest in the use of multiple levels to increase signaling bandwidth without increasing clock frequency. Signaling with multiple voltage levels uses lower fundamental frequencies than binary sig- naling at the same data rate, offering the potential of higher performance in systems which have limited bandwidth. In order to achieve this performance, however, circuit improvements are needed or the reduced signal swing directly impacts the system signal-to-noise ratio (SNR). Previous work in multi-pulse-am- plitude modulation (PAM) has concentrated on point-to-point links [1], [2] or LAN applications [3], [4]. This work studies the use of multi-PAM signaling in parallel bussed systems; in particular, printed-circuit-board-based multidrop systems where low latency is important. Before seriously considering any system configuration, the channel transfer function must first be understood. Block di- agrams of simple single and multidrop system configurations and accompanying channel models are shown in Fig. 1. In the first case (Low-LC) the master package and electrostatic dis- charge (ESD) parasitics are set to have good characteristics (L nH, C pF) like those of higher cost packaging such as flip-chip. In the N-drop case, the master is set to have the Manuscript received August 1, 2000; revised December 1, 2000. J. L. Zerbe, P. S. Chau, C. W. Werner, T. P. Thrush, H. J. Liaw, and K. S. Donnelly are with Rambus Incorporated, Los Altos, CA 94022 USA (e-mail: Jared@rambus.com). B. W. Garlepp is with Silicon Laboratories, Austin, TX 78735 USA. Publisher Item Identifier S 0018-9200(01)03026-8. (a) (b) (c) Fig. 1. (a) Multidrop system diagram. (b) Low-LC. (c) Multidrop simulation models. poorer parasitic values (L nH, C pF) more typical of lower cost ball-grid-array (BGA) style packaging and typ- ical ESD structures in 0.25- m ASIC processes. All cases use FR4 with 16 mm of master lead-in trace and 18-mm segments for loaded trace. The total trace length for a four-drop system is 10 cm. It is important to also consider the effects of device sub- strate resistance when modeling channel characteristics to avoid unrealistic resonances [8]. Simulated channel transfer characteristics of these different system configurations are shown in Fig. 2, a plot of normalized magnitude versus frequency. Several interesting effects can be observed in this figure. The first is the effect of the master para- sitics, the singular difference between the Low_LC and 1_drop curves. The Low_LC master channel shows good transfer char- acteristics and experiences very little loss up to 1 GHz. The 1_drop system, however, begins to roll off around 400 MHz, caused by the pole created by the master package silicon drop- ping from 2 GHz to 600 MHz. The second interesting effect to note is that of multiple devices or drops along the bus. As each 0018–9200/01$10.00 © 2001 IEEE