Indonesian Journal of Electrical Engineering and Computer Science Vol. 30, No. 3, June 2023, pp. 1420~1427 ISSN: 2502-4752, DOI: 10.11591/ijeecs.v30.i3.pp1420-1427  1420 Journal homepage: http://ijeecs.iaescore.com Low leakage decoder using dual-threshold technique for static random-access memory applications R. Krishna 1 , Punithavathi Duraiswamy 2 1 Department of Electronics and Communication Engineering, Bangalore Institute of Technology, Bengaluru, India 2 Department of Electronics and Communication Engineering, M S Ramaiah University of Applied Sciences, Bengaluru, India Article Info ABSTRACT Article history: Received Dec 24, 2022 Revised Feb 1, 2023 Accepted Feb 4, 2023 Decoders are one of the significant peripheral components of static random- access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method- at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively. Keywords: CMOS Decoders Dual threshold Leakage power NAND gate SRAM This is an open access article under the CC BY-SA license. Corresponding Author: R. Krishna Department of Electronics and Communication Engineering, Bangalore Institute of Technology Bengaluru, India Email: rkbit1971@gmail.com 1. INTRODUCTION CMOS technology scaling provides faster and high-performance devices, however, the power efficiency starts degrading due to the domination of leakage power in lower technology nodes [1]–[15]. Leakage or static power is a power consumed when the circuit is not functional. Nanoscale designs often employ optimization techniques to reduce power, area and improve circuit performance. Leakage power, data stability and speed of the circuit are the major requirements in today’s static random-asccess memory (SRAM) design. However, maintaining the desired stability and reducing the leakage power is a challenging task. At lower technology nodes, read static noise margin (read stability) and write static noise margin (write ability) and functional failures of SRAM cell can be minimized by applying read and write enhancement techniques. Leakage power can be reduced by circuit design techniques [13]. In SRAM, one of the essential components are address decoders. The decoder design plays a significant role in determining the power consumption and access time of the memory [2]–[6]. There are solutions available in literature for reducing the leakage power of circuits [7]–[19]. Conventisonal decoders are implemented using AND gate. The problem with conventional design is AND gate cannot be directly derived in CMOS technology [6]. Moreover, when fan-in more than 4,