This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 High-Mobility CVD-Grown Ge/Strained Ge 0.9 Sn 0.1 /Ge Quantum-Well pMOSFETs on Si by Optimizing Ge Cap Thickness Yu-Shiang Huang, Ya-Jui Tsou, Chih-Hsiung Huang, Chih-Hao Huang, Huang-Siang Lan, Chee Wee Liu, Senior Member, IEEE , Yi-Chiau Huang, Hua Chung, Chorng-Ping Chang, Fellow, IEEE , Schubert S. Chu, and Satheesh Kuppurao Abstract — The high peak mobility of 509 cm 2 /V · s of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and sur- face roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indi- cating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface. Index Terms— Cap thickness dependent of mobility, GeSn, low-frequency (LF) noise, strain. I. I NTRODUCTION H IGH hole mobility channels such as SiGe [1]–[3], Ge [4]–[8], and GeSn [9]–[12] can increase drive current of pMOSFETs. Moreover, the epitaxial biaxial compressive strain breaks the degeneracy of heavy-hole and light-hole bands of GeSn and results in the rise of light-hole band along channel 〈110〉 direction to reduce effective mass [11], [12]. The increasing Sn content of GeSn further reduces the effec- tive mass of light-holes at zone center as compared with the Ge [13]. Therefore, the GeSn has become a promising p-channel material for high-performance logic circuit. Manuscript received April 11, 2017; accepted April 16, 2017. National Taiwan University group is supported by the Ministry of Sci- ence and Technology, Taiwan under Grant 105-2622-8-002-001, Grant 103-2221-E-002-232-MY3, and Grant 103-2221-E-002-253-MY3. The review of this paper was arranged by Editor W. Tsai. (Corresponding author: C. W. Liu.) Y.-S. Huang, Y.-J. Tsou, C.-H. Huang, C.-H. Huang, and H.-S Lan are with the Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. C. W. Liu is with the Department of Electrical Engineering, Graduate Institute of Electronics Engineering, Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taipei 106, Taiwan, and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan (e-mail: cliu@ntu.edu.tw). Y.-C. Huang, H. Chung, C.-P. Chang, S. S. Chu, and S. Kuppurao are with the Applied Materials Inc., Sunnyvale CA 94085, USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2017.2695664 A critical issue for GeSn is the thermal stability due to the large covalent radius and low surface energy of Sn [14]–[16]. The surface segregation of Sn was observed after the thermal treatment at 580 °C, 500 °C, and 280 °C with the Sn content of 7.8% [17], 8.5% [18], and 17% [19], respectively. In order to realize the high performance of MOSFETs with high Sn content, low thermal budget is preferred in the fabrication to prevent the Sn segregation. Surface passivation of GeSn is the key to achieve the high mobility of GeSn MOSFETs. Si cap (∼1 nm) on SiGe can reduce the interface trap density ( D it ) and be a barrier to separate the carriers from oxide/interface charges to reduce Coulomb scattering and surface roughness scattering [20]. Low-temperature Si 2 H 6 passivation of GeSn surface was used to form an ultrathin SiO 2 /Si layer to enhance the interface quality and improve the mobility of GeSn pMOSFETs [11], [12], [21]–[28]. Due to the large lattice mismatch between Si and GeSn, the defects such as stacking faults and disloca- tions can be generated at the Si/GeSn interface to degrade the mobility [29], [30]. In this paper, we study Ge cap/GeSn/Ge quantum-well (QW) structure comprehensively to reduce the Coulomb scattering and surface roughness scattering. Note that Ge passivation can confine the holes in GeSn channels due to sufficient valence band discontinuity (E v ), but might not work for electrons due to small E c . To further boost the ON current and mobility, the Ge hole effective mass was reduced and the ON current and mobility was enhanced by external uniaxial mechanical strain [8], [31]. The low-frequency (LF) noise is used to probe the defects in the dielectrics and channels [32], [33]. The carrier num- ber fluctuation (CNF) due to carrier trapping/detrapping near the oxide/channel interface, and correlated mobility fluc- tuation (CMF) caused by Coulomb scattering are report- edly responsible for the noise generation [34]. LF noise of Si pMOSFETs [34], [35] and Ge pMOSFETs was stud- ied [32], [33], [36]–[40]. To the best of our knowledge, the LF noise of the GeSn channels has not been reported. In this paper, we optimize Ge cap thickness on GeSn to enhance interface quality and confine carriers in GeSn QW to reach high mobility of chemical vapor deposition (CVD)- grown GeSn channel pMOSFETs. The external uniaxial strain response and LF noise are also investigated. 0018-9383 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.