Investigation of Lateral Charge Distribution of 2-bit SONOS Memory Devices Using Physically Separated Twin SONOS Structure Byung Yong Choi*, Choong-Ho Lee 1 , Yong Kyu Lee 2 , Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park, Dong-Won Kim 1 , Suk-Kang Sung 1 , Se Hoon Lee 1 , Byung-Kyu Cho 1 , Tae-Yong Kim 1 , Eun Suk Cho 1 , Jong Jin Lee 1 , and Donggun Park 1 ISRC and School of Electrical Engineering and Computer Science, Seoul National University San #56-1, Shinlim-Dong, Kwanak-Ku, Seoul 151-742, Korea Tel: +82-31-209-9413 Fax: +82-31-209-9861 *E-mail: byungyong.choi@samsung.com 1 – Device Research Team, Semiconductor Research Center, Samsung Electronics Co., Ltd. Yongin-City, Gyeonggi-Do 449-711, Korea 2 – Department of Electrical Engineering, Stanford University, Stanford, CA 94305-4070, USA ABSTRACT The lateral charge distribution on 2-bit SONOS memory can be readily characterized using physically separated twin SONOS structure. The damascene gate and outer sidewall process successfully contribute to make the twin SONOS structure down to 80nm gate regime. Its lateral charge distribution is estimated through the SS and V th shifts for forward and reverse reading and confirmed by the comparison with a conventional (non-separated) SONOS structure. INTRODUCTION As the localized charges in a silicon-oxide-nitride- oxide-silicon (SONOS) memory are used to perform 2-bit/cell memory characteristics, the understanding of lateral charge distribution that is normally formed by Channel Hot Electron (CHE) and Hot Hole (HH) injection methods becomes more important to determine the scalability of gate length in a cell transistor [1-3]. Recently, the experimental characterization of laterally distributed charges has been carried out by the charge-pumping (CP) measurements. But the CP method is not pertinent for a mass production line due to its continuous long stress time and cycling requirements. To overcome this problem, a simple method using subthreshold slope (SS) and V th shifts of SONOS devices has been introduced. During this characterization, the lateral width of injected charges can be measured by the amounts of reverse V th shifts and SS degradation and the correlation with 2D device simulation [1]. But, it is too difficult to characterize the lateral charge distribution in a nanoscale structure, since it can not avoid the bit interference issue between associated bits. To solve these kinds of problems, we have developed twin SONOS memory structure with physically separated storage nodes [2]. In this novel structure, the width of laterally distributed charges is simply determined by the control of storage node size during its fabrication process. In this paper, we show the lateral charge distribution results of 80nm gate SONOS memory devices by introducing physically separated twin SONOS structure and measuring SS and V th shifts of both forward and reverse reading schemes [2-4]. DEVICE FABRICATION Fig. 1 shows the schematic diagram and their lateral charge distribution of (a) conventional (non-separated) and (b) twin (physically separated) SONOS devices that are characterized in this work. Those devices have the same geometric conditions including gate length (80nm), channel width (100nm), and O/N/O thickness (3.2/4.5/6.8nm). The fabrication process of twin SONOS device was briefly summarized in Fig. 2. In the fabrication process, the twin SONOS devices have undergone the damascene gate process to make physically separated structure and outer sidewall process to control the size of storage nitride, as shown in Fig. 3(a) ~ (d). During this poly-Si outer sidewall process, we can control the size of nitride storage node through the combination of deposited poly-Si thickness and its over-etching condition. The width of nitride storage node eventually determines the lateral dimension of injected charge distribution. Fig. 3(d) shows the oxide stained cross-sectional view of 80nm gate twin SONOS memory structure with 20nm storage nodes when its outer poly-Si sidewall process is completed. RESULTS AND DISCUSSION In Fig. 4, we compare the I d -V g characteristics between (a) conventional and (b) twin SONOS 2006 International Conference on Microelectronic Test Structures 1-4244-0167-4/06/$20.00 ©2006 IEEE 47