Accepted Manuscript A High-Performance, Resource-Efficient, Reconfigurable Parallel-Pipelined FFT Processor for FPGA Platforms Ngoc Hung Nguyen , Sheraz Ali Khan , Cheol-Hong Kim , Jong-Myon Kim PII: S0141-9331(17)30278-8 DOI: 10.1016/j.micpro.2018.04.003 Reference: MICPRO 2674 To appear in: Microprocessors and Microsystems Received date: 31 May 2017 Revised date: 22 March 2018 Accepted date: 12 April 2018 Please cite this article as: Ngoc Hung Nguyen , Sheraz Ali Khan , Cheol-Hong Kim , Jong-Myon Kim , A High-Performance, Resource-Efficient, Reconfigurable Parallel-Pipelined FFT Processor for FPGA Platforms, Microprocessors and Microsystems (2018), doi: 10.1016/j.micpro.2018.04.003 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.