International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.2, April 2016 DOI : 10.5121/vlsic.2016.7201 1            Sai Praveen Kadiyala and Debasis Samanta School of Information Technology, Indian Institute of Technology, Kharagpur ABSTRACT Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale high performance circuits. Yet, due to high switching activity they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and Domino logic styles. For a given circuit, we extract the unate and binate components using a unate decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power, area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and 22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications. KEYWORDS Domino Logic, High Performance Architecture, Boolean Decomposition, Unate function, Low Power Circuit 1. INTRODUCTION Recent trends show that there is a steep rise in the usage of battery operated handheld gadgets [1], [2], [3], [4]. This is posing increasing demands for devices operating at low power and high speed [5], [6]. With custom made chips coming into focus, the designers are pushing more and more functionalities on a single chip [7], [8], [9]. In fact, designers are now pushing billions of transistors in a single chip [10]. This increase the density of the chip and further give rise to problems like thermal variations, process variations, packaging, cooling issues etc. [11], [12], [13], [14]. This necessitates the synthesis of circuits with low power dissipation, without compromise in speed. Static CMOS logic style is often the choice of designers for designing low power circuits. This is because it is simple to fabricate, has good input/output decoupling and with lower switching activity. Circuits with this logic style are robust in nature and have good noise margins. Pass transistor logic (PTL), another style of static logic family, also finds good application in small scale designs. This logic is known for its low area overhead and ease for implementation. A number of attempts have been made to synthesize circuits using PTL [15], [16], [17], [18], [19]. Though static CMOS is used in low power circuits, it has inherent drawbacks. This style requires double the device count compared to other logic styles. The presence of bulky PMOS transistors in the charging path makes this logic style slow. Although, PTL offers less area and reduced noise margins, it has voltage degradation problem due to threshold voltage offset. As a consequence