0741-3106 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2019.2945474, IEEE Electron Device Letters > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract—The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The Vt difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher Vt difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The Vt difference increases with the increasing channel number and nanosheet width. Index Terms—Vertically stacked nanosheets, gate-all-around (GAA) MOSFETs, self-heating, threshold voltage (Vt). I. INTRODUCTION ertically stacked Si nanosheet (NS) gate-all-around MOSFETs (GAAFETs) have been reported as candidates for 5nm and beyond [1-5] due to the better gate control [5- 6] and larger Ion at the same footprint [2, 4-6] as compared to FinFETs. However, the inherent asymmetry of vertically stacked channels makes it unlikely to have the same junction temperature (Tj) among different channels, yielding the Vt difference (the difference between the highest and lowest Vt among the channels) intrinsically. This self-heating induced Vt difference is reported for the first time, apart from the Vt variations due to process imperfections [7-11], such as line edge roughness, metal gate granularity, and random dopant fluctuation. Moreover, the reported self-heating effect in the vertically stacked Si NS GAAFETs [12-16] did not consider the high thermal resistivity of SiGe S/D due to alloy scattering [17], S/D geometry by epitaxy, and all the interfacial thermal resistances (ITR) [18]. In this work, the comprehensive thermal modeling of vertically stacked Si NS GAAFETs by TCAD simulation [19] considering the boundary [20]/alloy scattering [17], embedded S/D geometry, and ITR [18] is investigated to obtain the Tj difference (the difference between the highest and lowest Tj) among the channels. The impacts of the pitch, NS width (Wsh), and DC/AC inputs on the Tj difference in both pFETs and nFETs are also studied. The intrinsic Vt difference among the channels due to the Tj difference is then calculated with the temperature dependence of Vt shift. II. THERMAL MODELING OF STACKED SI NS GAAFETS The self-heating of the vertically stacked Si NS GAAFET (Fig. 1) is simulated by TCAD considering the device geometry and the material thermal properties (Table I). The pitch is the vertical distance between the bottoms of the adjacent channels, and the offset is the vertical distance between the bottom of the1 st channel and the top of the channel stopper (Fig. 1). The channel is ordered in sequence from the bottom to top. The ITR is included in TCAD by inserting a virtual layer with thermal resistance (Rth) equal to ITR at the interface between different materials. The embedded SiGe and Si:P S/Ds have (1  11) and (11  1) facets just contacting the top NS corners to minimize the S/D size. Self-Heating Induced Interchannel V t Difference of Vertically Stacked Si Nanosheet Gate-All- Around MOSFETs Chia-Che Chung, Hung-Yu Ye, H. H. Lin, W. K. Wan, M.-T. Yang, and C. W. Liu, Fellow, IEEE V TiN/W TiN/W SiGe/TiN SiGe/TiN Si/SiGe Si/SiGe Si/SiGe Si/SiGe L S/D Pitch Offset Si/SiGe Si/SiGe Channel stopper Si 0.45 Ge 0.55 Si TiSi x TiN SiO 2 TiAlN W HfO 2 (11  1) S/D just contact the top NS 1 st 2 nd 3 rd Fig. 1. A vertically stacked Si NS pGAAFET for 5nm node [2] considering the ITR and diamond-shaped S/D. For nFET, Si:P S/D and TiAlN workfunction metal are used. TABLE I. INTERFACIAL THERMAL CONDUCTIVITY AND THERMAL CONDUCTIVITY IN VERTICALLY STACKED SI NS GAAFET. Interfacial thermal conductivity (GW/K/m 2 ) Thermal conductivity (W/K/m) W 174 [18] Si/TiN (SiGe/TiN) 1.10 [21] TiAlN 19.3 [18] HfO 2 2.3 [18] TiN/W 0.40 [21] SiO 2 1.4 [18] Si/Ge (Si/SiGe) 0.33 [22] Si 13 [20] Si/Oxide 1.10 [23] Si 0.45 Ge 0.55 2.0 [17] Oxide/TiN 1.03 [21] TiSi x 19.3 [18] This work was supported by the Ministry of Science and Technology, Taiwan (108-2218-E-002-027 and 108-2622-8-002-016) and the Ministry of Education, Taiwan (NTU-CC-108L891701). Chia-Che Chung and Hung-Yu Ye are with the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. H. H. Lin, W. K. Wan, and M.-T. Yang are with MediaTek Inc., Hsinchu 300, Taiwan. C. W. Liu is with the Department of Electrical Engineering, Graduate Institute of Electronics Engineering, Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taipei 106, Taiwan (e-mail: cliu@ntu.edu.tw).