International Journal of Computer Applications (0975 – 8887) Volume 66– No.9, March 2013 11 Survey on Various Types of Power in DLL Ranjana Kumari Mishra M.Tech Scholar Rajesh Nema Associate Professor Teena Raikwar Assistant Professor NRI Institute of Information Science & Technology Bhopal (M.P)-462021, India ABSTRACT A low power analysis of the jitter bounded is presented in this paper. Digital Delay Locked Loop (DLL) are commonly used for clock synchronization in modern ICs because of their superior stability and process portability. The DLL has a graduated course delay line and a phase interpolating fine delay line. Keywords- All digital delay locked loop (ADDLL), clock generator, Jitter, agilent E4422B, Oscilloscope 54833D. 1. Introduction There are two components that establish the amount of power dissipated in a CMOS circuit. These are: Figure 1.Block Diagram of power dissipation Power dissipation has skyrocketed due to transistor scaling, chip transistor counts and clock frequencies.  Static dissipation due to leakage current or other current drawn continuously from the power supply.  Dynamic dissipation due to  Switching transient current.  Charging and discharging of load capacitances. A. Static Dissipation Static dissipation due to –  Sub threshold conduction through OFF transistors  Tunneling current through gate oxide  Leakage through reverse-biased diodes  Contention current in ratioed circuits B. Dynamic Dissipation  Charging and discharging of load capacitances  Short circuit current while both PMOS and NMOS networks are partially ON P total = P static + P dynamic 2. Delay Locked Loop: In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase locked loop (PLL), with the main difference being the absence of an internal voltage controlled oscillator, replaced by a delay line. As the clock frequency of synchronous VLSI circuits increases, there arises a greater need to correctly align system clocks. Emphasis must be placed on suppressing clock skew and jitter. As the clock period is reduced, if jitter and skew remain the same, the total clock phase error is increased. This can affect many aspects of a synchronous system, including setup and hold times, data access times, and accuracy of internal control signals. To eliminate clock skew, a simple, fixed-delay circuit might be used, but with variations in process, voltage, and temperature (PVT), the delay time would vary. Also, if the clock period were to change, the delay time would need to be modified. Therefore, a dynamic, variable delay circuit is needed to eliminate system clock skew across PVT and varying clock frequencies. A Delay-Locked Loop (DLL) is such a circuit. Fig. 1 shows a DLL being used to ensure proper synchronization between a synchronous memory device and a memory controller. In this simple example, the DLL within the memory device is used to ensure that there is no skew between the control clock generated by the controller and the data coming out of the memory. This is especially important when a fast control clock is used; if skew remains in the output data while using a fast clock rate, the memory controller might have a difficult time distinguishing from one bit to the next being clocked from the memory. As synchronous memory moves to other standards, such as double-data rate (DDR) devices, where data is clocked out on both the rising and falling edges of the control clock, the problem of internal clock skew is compounded. A DLL can solve this problem by ensuring proper synchronization across PVT as well as variations in the control clock frequency [1], [2]. POWER DISSIPATION Static Dissipation Dynamic Dissipation  Sub-threshold current  Gate leakage  Reverse-biased diode current  Contention current  Capacitive switching  Gate leakage  Short circuit