A Carrier Redistribution PWM for Dual Inverter with Separated DC Circuits Martin Votava, Tomas Glasberger Regional Innovation Centre for Electrical Engineering (RICE) University of West Bohemia in Pilsen, Czech Republic Abstract—This paper deals with a proposal of a carrier redistribution PWM and its comparison with a phase disposition PWM (PDPWM) and carrier redistribution PWM for a multilevel converter dedicated to high power medium voltage electric drives. The converter topology is based on a cascaded connection of two-level inverters, the so called dual inverter. The well known phase disposition PWM for multilevel converters is modiﬁed for the above mentioned topology and its derivation as carrier redis- tribution PWM (CRPWM) strategy is employed. The proposed CRPWM enables the reduction of unbalanced load of the power electronics switches and increasing in the maximum output power rate. The functionality of the proposed PWM strategy has been veriﬁed on a simulation model of the converter as well as by experiments. The proposed PWM strategy has been compared with the standard PDPWM according to selected criteria such as total power losses, balanced load of switching devices and THD of phase load voltage waveforms. Index Terms—Multilevel converter, dual inverter, car- rier redistribution, phase disposition, PWM, power losses, THD. I NTRODUCTION As the demands of industry applications on power electronics have increased in last decades, the mul- tilevel converter (MLC) topologies became popular. In multilevel conﬁgurations, the dc voltage is divided among a number of components, therefore the voltage stress on power semiconductors is lower, the output voltage steps during switching is lower and the ampli- tudes of harmonics in side band are reduced [1]. There are many known topologies of multilevel con- verters. The best known typical conﬁgurations are neu- tral point clamped converters (NPC), ﬂying capacitors converters (FLC), cascaded H-bridges (CHB), modular multilevel converters (M2LC) [2], [3], [4]. Each of the mentioned conﬁgurations has different advantages. The advantage of the M2LC is a simple process of scaling output voltage levels by linear addition of identical modules. However, the conduction losses of the M2LC are increased by a circulating current caused by un- balanced capacitor voltages. Moreover, the capacitor voltage ripple depends on the output frequency and it is higher for the lower output frequencies. NPC, FLC and CHB do not have any circulating currents, however in the FLC and NPC respectively the additional number of elements is required. The This research has been supported by the European Regional Development Fund and the Ministry of Education, Youth and Sports of the Czech Republic under the Regional Innovation Centre for Electrical Engineering (RICE), project No. CZ.1.05/2.1.00/03.0094, by TA CR under project No. TE01020455 and by project No. SGS- 2015-038. advantage of the FLC and the CHB over the NPC is the number of redundant switching combinations which allow a dc circuit voltage balancing [5]. Moreover, the CHB does not have any additional capacitors or diodes. However, the main drawback of the CHB is requirement of separated dc circuit per each cell [6]. A simple modular solution to decrease the number of dc circuits can be a multilevel converter represented by the so called dual two-level inverter connection with separated dc sources with equivalent dc sources the dc voltage balancing is not an issue [7]. These topologies could be controlled by several modiﬁcations of pulse width modulation known as phase shifted PWM (PSPWM), phase disposition PWM (PDPWM) and space vector PWM [8], [9], [10]. Previous research has demonstrated that the average transistor switching frequency of PDPWM is lower than the average transistor switching frequency of PSPWM. However, the disadvantage of the PDPWM is an unbalanced load of IGBTs [11]. Using the PDPWM, the unbalanced voltage in the dc circuit can appear, and this leads to higher voltage stress on switching elements and the shorter lifetime of capaci- tors [12]. Therefore, several modiﬁcations of PDPWM techniques, such as the selective loop bias mapping PDPWM (SLBM-PDPWM), the carrier redistribution PWM and the multiple carrier modulation with dc stack current injection modulation have been developed and presented in [13], [14], [15]. These methods are able to reduce the unbalance of capacitor voltages for several MLC topologies including FLC, NPC, CHB. As shown in chapter , some of these modiﬁcations can be used to achieve balanced load of IGBTs and to increase the maximum output power rate of the dual level inverter with equal separated dc sources. The goal of this paper is to propose a CRPWM based control for the dual inverter and to verify that the proposed CRPWM has the balanced load of semi- conductor switches (IGBTs). The paper also seeks to compare this control method with the PDPWM for the dual inverter with separated dc link multilevel topology. DUAL I NVERTER TOPOLOGY The topology of the multilevel converter based on a dual inverter topology is shown in Fig. 1. This topology requires lower number of dc voltage sources (dc capacitors) and does not have any clamped diode or capacitors. Furthermore, the dual inverter does not need to be connected to the middle of dc link capacitors, ISBN 978-80-261-0386-8, c  University of West Bohemia, 2015